Abstract: Provided are a method for managing network slice connection, a terminal and a computer-readable storage medium. The method for managing network slice connection includes: obtaining connection request information transmitted by a terminal application in a case where the terminal application initiates a network slice connection request; performing an authentication process on the terminal application initiating the network slice connection request; and in response to the terminal application passing the authentication process, enabling the terminal application to connect to a network slice according to the connection request information.

Abstract: The present disclosure provides an extracorporeal focused ultrasound treatment device for a pelvic disease. The treatment device includes an ultrasonic transducer and a treatment couch. Sound emitting surface of the ultrasonic transducer is a spherical surface having a first notch, a second notch and a third notch, the first notch and the second notch are respectively positioned at two intersections of the spherical surface and a diameter perpendicular to the main great circle, and the third notch connects the first notch with the second notch; a cross-section of the sound emitting surface parallel to the main great circle is in a shape of an arc; and an ultrasonic wave generated by the sound generation unit is focused at a center of the sphere corresponding to the sound emitting surface. The treatment couch is configured for a human body to lie in a lithotomy position.

Abstract: The lesion locating method includes locating a lesion by locating a mark on a body surface; using a camera in locating to assist an ultrasound probe for locating; forming a reference view according to data acquired in real time by the camera, where the reference view has a preset size, and a virtual mark point corresponding to the mark is formed in the reference view; and determining, according to a position of the virtual mark point in in the reference view and an actual positional relationship of the camera and the ultrasound probe, an actual locating trajectory that enables a center line of the ultrasound probe to coincide with the mark. The camera is configured to acquire camera data to form the reference view, and then assists the ultrasound probe for locating with the reference view.

Abstract: The present disclosure provides a radiation inspection apparatus and a radiation inspection method. The radiation inspection apparatus includes: a radiation inspection device comprising a ray source and a detector that cooperates with the ray source to perform scanning inspection on an object to be inspected, the radiation inspection device having an inspection channel for the object to be inspected to pass through when scanning inspection is performed thereon; and traveling wheels provided at the bottom of the radiation inspection device to enable the radiation inspection apparatus to travel in an extension direction of the inspection channel, and the traveling wheels are configured to rotate 90° to enable the radiation inspection apparatus to travel in a direction perpendicular to the extension direction of the inspection channel.

Abstract: Provided are a method for managing network slice connection, a terminal and a computer-readable storage medium. The method for managing network slice connection includes: obtaining connection request information transmitted by a terminal application in a case where the terminal application initiates a network slice connection request; performing an authentication process on the terminal application initiating the network slice connection request; and in response to the terminal application passing the authentication process, enabling the terminal application to connect to a network slice according to the connection request information.

Abstract: The present disclosure provides a radiation inspection apparatus and a radiation inspection method. The radiation inspection apparatus includes: a radiation inspection device comprising a ray source and a detector that cooperates with the ray source to perform scanning inspection on an object to be inspected, the radiation inspection device having an inspection channel for the object to be inspected to pass through when scanning inspection is performed thereon; and traveling wheels provided at the bottom of the radiation inspection device to enable the radiation inspection apparatus to travel in an extension direction of the inspection channel, and the traveling wheels are configured to rotate 90° to enable the radiation inspection apparatus to travel in a direction perpendicular to the extension direction of the inspection channel.

Abstract: The present invention provides a comparator circuit applicable to a high-speed pipeline ADC. The comparator circuit includes a switch capacitor circuit, a pre-amplification circuit, and a latch circuit. The pre-amplification circuit includes a pre-amplifier, a resistance-adjustable device, two switches. The latch circuit includes a differential static latch, a first capacitor, a second capacitor, and a third switch. The transmission rates of a sampling phase and a setup phase can be increased.

Abstract: The present invention provides a comparator circuit applicable to a high-speed pipeline ADC. The comparator circuit includes a switch capacitor circuit, a pre-amplification circuit, and a latch circuit. The pre-amplification circuit includes a pre-amplifier, a resistance-adjustable device, two switches. The latch circuit includes a differential static latch, a first capacitor, a second capacitor, and a third switch. The transmission rates of a sampling phase and a setup phase can be increased.

Abstract: The present disclosure provides an extracorporeal focused ultrasound treatment device for a pelvic disease. The treatment device includes an ultrasonic transducer and a treatment couch. Sound emitting surface of the ultrasonic transducer is a spherical surface having a first notch, a second notch and a third notch, the first notch and the second notch are respectively positioned at two intersections of the spherical surface and a diameter perpendicular to the main great circle, and the third notch connects the first notch with the second notch; a cross-section of the sound emitting surface parallel to the main great circle is in a shape of an arc; and an ultrasonic wave generated by the sound generation unit is focused at a center of the sphere corresponding to the sound emitting surface. The treatment couch is configured for a human body to lie in a lithotomy position.

Abstract: The present invention provides a chip ESD protection circuit, includes an integrated circuit layer and a conductive layer. A first ground bonding pad that is connected to a first ground wire of a first power domain is disposed on each of the first power domain and a second power domain in the integrated circuit layer. The first ground bonding pads are bonded to the conductive layer. A second power clamping unit is disposed on the second power domain. A first end of the second power clamping unit is connected to a second power wire of the second power domain, and a second end thereof is connected to the first ground wire or a second ground wire of the second power domain. According to the chip ESD protection circuit, the ESD protection capability of a chip can be improved. The occupied area of the chip is reduced.

Abstract: A comparator offset voltage self-correction circuit is disclosed. A comparator offset voltage which is caused by the semiconductor process parameter randomness also has randomness. Due to the randomness of the comparator offset voltage, a reference voltage of a parallel comparator in a parallel-conversion-type analog-to-digital converter is uncertain. If the comparator offset voltage is large, the parallel-conversion-type analog-to-digital converter may even have a functional error. The comparator offset voltage self-correction circuit provided in the present invention can correct a random offset voltage of a comparator to meet requirements.

Abstract: An error compensation correction device for a pipeline analog-to-digital converter includes a correction pipeline stage and a conventional pipeline stage. For each correction pipeline stage, a corresponding error estimation circuit, a level edge detection circuit, a random level generation circuit, and MUX circuit being provided. The present disclosure can track and correct non-ideal properties and mismatching errors in real time over time along with the change of the surroundings without interrupting the ADC normal work of the pipeline. Thus the correction value is closer to the real situation.

Abstract: A sampling device includes a switch capacitor circuit. First ends of two switches are respectively connected to an input signal. Second end of the first switch is connected to an upper plate of a first capacitor. Second end of the second switch is connected to a lower plate of a second capacitor. A connection node connecting a lower plate of the first capacitor to an upper plate of the second capacitor is connected to a power source. The first ends of a third switch and a fourth switch are respectively connected to an input common-mode voltage. A second end of the third switch is connected to the upper plate of the first capacitor. A second end of the fourth switch is connected to the lower plate of the second capacitor. The connection node is connected to the power source. Thus, an output common-mode voltage of the sampling device is adjustable.

Abstract: A high-speed low-power-consumption dynamic comparator includes a latch, an AND gate, a delay unit, and an XNOR gate. According to the high-speed low-power-consumption dynamic comparator, the output signal is generated through the XNOR gate from the comparator output signals Dp and Dn. The output signal and the control signal clk1 generate the control signal of the NMOS transistor P10 through the AND gate, so that the problem of static power consumption in a conventional comparator is solved.

Abstract: A comparator offset voltage self-correction circuit is disclosed. A comparator offset voltage which is caused by the semiconductor process parameter randomness also has randomness. Due to the randomness of the comparator offset voltage, a reference voltage of a parallel comparator in a parallel-conversion-type analog-to-digital converter is uncertain. If the comparator offset voltage is large, the parallel-conversion-type analog-to-digital converter may even have a functional error. The comparator offset voltage self-correction circuit provided in the present invention can correct a random offset voltage of a comparator to meet requirements.

Abstract: A sampling device includes a switch capacitor circuit. First ends of two switches are respectively connected to an input signal. Second end of the first switch is connected to an upper plate of a first capacitor. Second end of the second switch is connected to a lower plate of a second capacitor. A connection node connecting a lower plate of the first capacitor to an upper plate of the second capacitor is connected to a power source. The first ends of a third switch and a fourth switch are respectively connected to an input common-mode voltage. A second end of the third switch is connected to the upper plate of the first capacitor. A second end of the fourth switch is connected to the lower plate of the second capacitor. The connection node is connected to the power source. Thus, an output common-mode voltage of the sampling device is adjustable.

Abstract: A high-speed low-power-consumption dynamic comparator includes a latch, an AND gate, a delay unit, and an XNOR gate. According to the high-speed low-power-consumption dynamic comparator, the output signal is generated through the XNOR gate from the comparator output signals Dp and Dn. The output signal and the control signal clk1 generate the control signal of the NMOS transistor P10 through the AND gate, so that the problem of static power consumption in a conventional comparator is solved.

Abstract: An error compensation correction device for a pipeline analog-to-digital converter includes a correction pipeline stage and a conventional pipeline stage. For each correction pipeline stage, a corresponding error estimation circuit, a level edge detection circuit, a random level generation circuit, and MUX circuit being provided. The present disclosure can track and correct non-ideal properties and mismatching errors in real time over time along with the change of the surroundings without interrupting the ADC normal work of the pipeline. Thus the correction value is closer to the real situation.

Abstract: The present invention provides a chip ESD protection circuit, includes an integrated circuit layer and a conductive layer. A first ground bonding pad that is connected to a first ground wire of a first power domain is disposed on each of the first power domain and a second power domain in the integrated circuit layer. The first ground bonding pads are bonded to the conductive layer. A second power clamping unit is disposed on the second power domain. A first end of the second power clamping unit is connected to a second power wire of the second power domain, and a second end thereof is connected to the first ground wire or a second ground wire of the second power domain. According to the chip ESD protection circuit, the ESD protection capability of a chip can be improved. The occupied area of the chip is reduced.

Abstract: A dither circuit for high-resolution analog-to-digital converters (ADCs) is presented, including a settable pseudorandom sequence generator, a trimming module, a trimmable digital-to-analog conversion circuit, a dither introduced circuit and a dither elimination circuit, wherein the settable pseudorandom sequence generator works to generate pseudorandom sequence signal uncorrelated to analog input signal and its output can be set, of which n bit output is taken as digital dither signal and n can be less than the quantization bit of the ADC; the trimming module works to determine the trimming signals for the trimmable digital-to-analog conversion circuit to convert the digital dither signal into analog dither signal precisely; the dither introduced circuit works to introduce the analog dither signal to the ADC; the dither elimination circuit works to remove the digital dither signal from the output of ADC. The dither circuit features less complexity and better dynamic performance for high-resolution ADC.