Patents by Inventor Bing Han

Bing Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11832455
    Abstract: The present application relates to display panel. An opening area of any one of sub-pixels of the first transitional display region is larger than an opening area of a same-colored sub-pixel of the first display region and is smaller than an opening area of a same-colored sub-pixel of the second display region. An interval between any two closest sub-pixels of a same color arranged in adjacent columns in the first display region is x; an interval between any two closest sub-pixels of a same color arranged in two adjacent columns respectively in the first transitional display region and the second display region is y; an interval between any two closest sub-pixels of a same color arranged in two adjacent columns in the second display region is z, wherein x?y?z. The present application also provides a display device.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: November 28, 2023
    Assignee: YUNGU (GU'AN) TECHNOLOGY CO., LTD.
    Inventors: Mingxing Liu, Ying Zhao, Bing Han, Shuaiyan Gan
  • Publication number: 20230374648
    Abstract: A mask and a mask assembly. The mask includes an evaporation region and a peripheral region. The evaporation region includes at least one evaporation opening. The peripheral region includes a solid region arranged around the evaporation region. The solid region includes a stress-relieving portion. The stress-relieving portion is arranged around the evaporation region and is distributed in a circumferential direction.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Applicant: Hefei Visionox Technology Co., Ltd.
    Inventors: Gongzheng ZANG, Wenxing LI, Weili LI, Bing HAN, Jishuai ZHANG, Yue QIU
  • Patent number: 11823891
    Abstract: A backside metallized compound semiconductor device includes a compound semiconductor wafer and a metal layered structure. The compound semiconductor wafer includes a substrate having opposite front and back surfaces, and a ground pad structure formed on the front surface. The substrate is formed with a via extending from the back surface to the front surface to expose a side wall of the substrate and a portion of the ground pad structure. The metal layered structure is disposed on the back surface, and covers the side wall and the portion of the ground pad structure. The metal layered structure includes an adhesion layer, a seed layer, a gold layer, and an electroplated copper layer that are formed on the back surface in such order. The method for manufacturing the backside metallized compound semiconductor device is also disclosed.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: November 21, 2023
    Assignee: XIAMEN SANAN INTEGRATED CIRCUIT CO., LTD.
    Inventors: Tsung-Te Chiu, Kechuang Lin, Houng-Chi Wei, Chia-Chu Kuo, Bing-Han Chuang
  • Publication number: 20230367596
    Abstract: An instruction prediction method and apparatus, a system, and a computer-readable storage medium relate to the field of computer technologies. The method includes: a processor obtains a plurality of to-be-executed first IBs, where any first IB includes at least one instruction to be sequentially executed, and the at least one instruction includes one branch instruction; searches, based on branch instructions included in the plurality of first IBs, at least one candidate execution path for a candidate execution path corresponding to the plurality of first IBs, where any candidate execution path indicates a jump relationship between a plurality of second IBs, and a jump relationship indicated by the candidate execution path corresponding to the plurality of first IBs includes a jump relationship between the plurality of first IBs; and predicts, based on the jump relationship between the first IBs, a next instruction corresponding to a branch instruction in each first D3.
    Type: Application
    Filed: May 9, 2023
    Publication date: November 16, 2023
    Inventors: Bing Han, Yongyu Chen, Nan Li, Taixu Tian
  • Publication number: 20230348736
    Abstract: Described herein are compositions for depositing a carbon-doped silicon containing film comprising: a precursor comprising at least one compound selected from the group consisting of: an organoaminosilane having a formula of R8N(SiR9LH)2, wherein R8, R9, and L are defined herein. Also described herein are methods for depositing a carbon-doped silicon-containing film using the composition wherein the method is one selected from the following: cyclic chemical vapor deposition (CCVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD) and plasma enhanced CCVD (PECCVD).
    Type: Application
    Filed: June 20, 2023
    Publication date: November 2, 2023
    Inventors: MANCHAO XIAO, XINJIAN LEI, RONALD MARTIN PEARLSTEIN, HARIPIN CHANDRA, EUGENE JOSEPH KARWACKI, BING HAN, MARK LEONARD O'NEILL
  • Patent number: 11800264
    Abstract: A system for sending data in an optical network comprising a plurality of source nodes and destination nodes is disclosed. In one aspect, a source node generates, in a spectral band that is associated with it, a multi-carrier optical data signal obtained by modulation of a source signal at a source wavelength and sends it in the form of single-band data bursts that can be associated with distinct source wavelengths. A single-band data burst comprises, in addition to payload data symbols (PL), a sequence of learning symbols (TS) composed of a plurality of learning symbols. A control unit belonging to the control plane of the optical network determines, for at least one of the source nodes, instants of sending of the single-band data bursts and source wavelengths to be used for sending these single-band data bursts, as a function of a path time of the data bursts between the source node and one of the destination nodes associated with the source wavelength.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: October 24, 2023
    Assignee: Orange
    Inventors: Bing Han, Paulette Gavignet, Erwan Pincemin
  • Patent number: 11798957
    Abstract: The present disclosure relates to an array substrate, a display panel, and a large glass panel. The array substrate includes a test structure. The test structure includes a substrate, and a first conductive layer, an insulating layer, a second conductive layer, and a passivation layer sequentially stacked on the substrate. The passivation layer is provided with at least one first groove, at least one second groove, and one third groove. An opening size of the third groove is greater than opening sizes of the at least one first groove and the at least one second groove. The first groove penetrates through the passivation layer and extends to the first conductive layer. The second groove penetrates through the passivation layer and extends to the second conductive layer. The third groove penetrates through the passivation layer and extends to the first conductive layer or the second conductive layer.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: October 24, 2023
    Assignee: HKC CORPORATION LIMITED
    Inventors: Bing Han, Jie Ran, Lidan Ye
  • Publication number: 20230324747
    Abstract: Disclosed are an array substrate, a display panel and a display. The array substrate is provided with a thin film transistor and a gate driving circuit. A trigger signal input terminal of the gate driving circuit corresponds to an output terminal of the thin film transistor, a first insulating layer is provided between a first metal layer corresponding to the output terminal of the thin film transistor and a second metal layer corresponding to the trigger signal input terminal of the gate driving circuit. A projected area of the first metal layer on the first insulating layer is partially overlapped with a projected area of the second metal layer on the first insulating layer.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 12, 2023
    Applicant: HKC CORPORATION LIMITED
    Inventors: Hongyan CHANG, Bing HAN, Haijiang YUAN
  • Patent number: 11768817
    Abstract: In an example embodiment, shards of a database are each stored in in-memory storage as multiple redundant distinct shard instances, but rather than a leader-follower paradigm each redundant shard instance is independent from one another. Each shard contains only an odd number of shard instances, and the number of shard instances is greater than or equal to three. This helps to ensure that enough shard instances are available at any one time to service requests.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: September 26, 2023
    Assignee: SAP SE
    Inventor: Bing Han
  • Publication number: 20230263769
    Abstract: An application of ellagic acid and a metabolic derivative urolithin compound thereof in preparation of an immunomodulatory medicine is provided. Classical animal models of autoimmunity and immunoregulation, such as experimental autoimmune encephalomyelitis, neuromyelitis optica mouse model, ulcerative colitis, and skin transplantation, are used as examples to conduct experiments from various aspects and perspectives, such as neurological function scores, histopathological changes of lesions, inflammatory factor expression, and pro-inflammatory cell numbers.
    Type: Application
    Filed: February 24, 2022
    Publication date: August 24, 2023
    Inventors: YUAN ZHANG, WENHUI QI, XING LI, BING HAN, PEIXIN SHEN
  • Patent number: 11725111
    Abstract: Described herein are compositions for depositing a carbon-doped silicon containing film comprising: a precursor comprising at least one compound selected from the group consisting of: an organoaminosilane having a formula of R8N(SiR9LH)2, wherein R8, R9, and L are defined herein. Also described herein are methods for depositing a carbon-doped silicon-containing film using the composition wherein the method is one selected from the following: cyclic chemical vapor deposition (CCVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD) and plasma enhanced CCVD (PECCVD).
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: August 15, 2023
    Assignee: Versum Materials US, LLC
    Inventors: Manchao Xiao, Xinjian Lei, Ronald Martin Pearlstein, Haripin Chandra, Eugene Joseph Karwacki, Bing Han, Mark Leonard O'Neill
  • Publication number: 20230247882
    Abstract: A display panel and a display device are provided. The display panel includes first color sub-pixels, second color sub-pixels, and third color sub-pixels. The first color sub-pixel is surrounded by a first safe region, the second color sub-pixel is surrounded by a second safe region, and the third color sub-pixel is surrounded by a third safe region. None of the first color sub-pixels, the second color sub-pixels, and the third color sub-pixels is provided in each of the first safe regions, the second safe regions and the third safe regions. The first safe region, the second safe region, and the third safe region have three different areas, respectively.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 3, 2023
    Applicants: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD., Wuhan Tianma Microelectronics Co., Ltd. Shanghai Branch
    Inventors: Bing Han, Gaojun Huang, Yu Xin
  • Publication number: 20230236727
    Abstract: This application provides a circuit, a chip, and an electronic device. The circuit includes a first processor and a first processing module connected to the first processor. The first processing module includes a second processor connected to a first memory. A transmission latency generated when the second processor performs read and write operations on the first memory is less than a transmission latency generated when the first processor communicates with the first processing module. Because the transmission latency generated when the second processor performs the read and write operations on the first memory is less than the transmission latency generated when the first processor communicates with the first processing module, a cost of a transmission latency of data in a bus can be reduced.
    Type: Application
    Filed: March 29, 2023
    Publication date: July 27, 2023
    Inventors: Taixu Tian, Bing Han
  • Publication number: 20230222841
    Abstract: The present invention proposes an ensemble deep learning method for identifying unsafe behaviors of operators in maritime working environment. Firstly, extract features of maritime images with the You Only Look Once (YOLO) V3 model, and then enhance a multi-scale detection capability by introducing a feature pyramid structure. Secondly, obtain instance-level features and time memory features of the operators and devices in the maritime working environment with the Joint Learning of Detection and Embedding (JDE) paradigm. Thirdly, transfer spatial-temporal interaction information into a feature memory pool, and update the time memory features with the asynchronous memory updating algorithm. Finally, identify the interaction between the operators, the devices, and unsafe behaviors with an asynchronous interaction aggregation network. The proposed invention can accurately determine the unsafe behaviors of the operators, and thus provide operation decisions for maritime management relevant activities.
    Type: Application
    Filed: May 18, 2022
    Publication date: July 13, 2023
    Inventors: Xinqiang Chen, Zichuang Wang, Yongsheng Yang, Bing Han, Zhongdai Wu, Chenxin Wei, Huafeng Wu, Yang Sun
  • Publication number: 20230222919
    Abstract: The present invention proposes a vessel traffic pattern identification method via data quality control and data compression. Firstly, assort a collection of Automatic Identification system (AIS) data points according to Mobile Service Identify (MMSI) code and sort each collection result by time ascending order, and then delete duplicated vessel AIS data points considering time stamp, latitude, longitude and vessel speed over ground, then segment vessel trajectories. Secondly obtain high-quality AIS data with an AIS data anomaly detection and repair and compress each vessel trajectory with the Douglas-Peucker algorithm. Thirdly, cluster vessel trajectories with the Quick Bundles algorithm, and identify maritime traffic pattern. The invention can efficiently identify vessel traffic patterns, and help maritime traffic management departments to accurately identify a traffic situation.
    Type: Application
    Filed: October 30, 2022
    Publication date: July 13, 2023
    Inventors: Xinqiang Chen, Qiuying Wang, Yongsheng Yang, Bing Han, Zhongdai Wu, Huafeng Wu, Yang Sun, Chaofeng Li, Jiangfeng Xian, Wei Liu
  • Publication number: 20230214084
    Abstract: A method for displaying an interface includes displaying first emoji information on an information display interface; and presenting a second emoji on the information display interface in response to the first emoji information being displayed on the information display and second emoji information being acquired. The first emoji information comprises an image and/or a description corresponding to a first emoji, and the second emoji information comprises an image and/or a description corresponding to the second emoji.
    Type: Application
    Filed: August 4, 2022
    Publication date: July 6, 2023
    Inventors: Bing HAN, Xinyi LI
  • Publication number: 20230194938
    Abstract: Provided is an array substrate, a manufacturing method for an array substrate, and a display panel. The array substrate includes a fist substrate base, common electrode lines, a color filter layer, and a planarization layer; the color filter layer includes first color filters and a second color filters, forming color filter channels therebetween on the common electrode lines, so as to avoid overlapping between the first color filters and the second color filters. The width of the common electrode lines is relatively small, ensuring a high aperture rate of the array substrate. Additionally, the array substrate further includes a planarization layer filled in the color filter channels, this minimizes the color filter channels to ensure flatness between the first color filters and the second color filters, so that etching residues in the color filter channels can be avoided when forming the pixel electrode layer.
    Type: Application
    Filed: November 28, 2022
    Publication date: June 22, 2023
    Applicant: HKC CORPORATION LIMITED
    Inventors: Shishuai HUANG, Bing HAN, Baohong KANG
  • Publication number: 20230191770
    Abstract: The present application discloses a cutting method for a display panel, a display panel and a display device, the cutting method for a display panel including a cutting stage of a side edge of a binding area and a cutting stage of a side edge of a non-binding area, the cutting stage of a side edge of a non-binding area includes steps of: aligning a cutter according to an alignment mark preset on the side edge of the non-binding area on the display panel, so that a cutter on a second substrate side is closer to a display area of the display panel than a cutter on a first substrate side, and cutting the first substrate and the second substrate by the cutter on the second substrate side and the cutter on the first substrate side respectively.
    Type: Application
    Filed: February 12, 2023
    Publication date: June 22, 2023
    Inventors: Qianqian YANG, Shishuai HUANG, Bing HAN, Haijiang YUAN
  • Publication number: 20230197734
    Abstract: A base substrate and a first metal layer laminated on the base substrate are included. A first laminated portion and a second laminated portion are arranged on and directly contact a side of the first metal layer. The first laminated portion includes a first insulating layer, a second metal layer, a second insulating layer and a first conductive layer. The first laminated portion is arranged with a first via. The second laminated portion includes a third insulating layer and a second conductive layer laminated on the third insulating layer. The second laminated portion is arranged with a second via. The first via is connected to the first conductive layer, the second via is connected to the second conductive layer, and the first conductive layer is connected to the second conductive layer. The second laminated portion is extended to reach an edge of the first metal layer.
    Type: Application
    Filed: November 24, 2022
    Publication date: June 22, 2023
    Inventors: HONGYAN CHANG, Zhenya Li, Guangjia Wang, Bing Han, Shishuai Huang, Xiaojie Wang, Haijiang Yuan
  • Publication number: 20230184703
    Abstract: A quantitative statistical characterization method of micron-level second phase in aluminum alloy based on deep learning is disclosed. The method includes obtaining a feature database of the standard sample, training the feature database by the image segmentation network U-Net based on deep learning to obtain a U-Net segmentation model, selecting the corresponding parameters of the optimal precision and establishing a U-Net target model; clipping the aluminum alloy image to be detected and inputting the clipped images into the U-net target model, obtaining the size, area and position information of the second phase through the connected region algorithm, carrying out statistical distribution of the data set combined with the mathematical statistical method, and restoring the position information to the surface of the aluminum alloy to be tested to obtain the full-field quantitative statistical distribution and visualization results.
    Type: Application
    Filed: April 13, 2021
    Publication date: June 15, 2023
    Applicant: Central Iron & Steel Research Institute
    Inventors: Dandan Sun, Bing Han, Weihao Wan, Haizhou Wang, Lei Zhao, Dongling Li, Caichang Dong