Abstract: A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape.

Abstract: A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape.

Abstract: A method for generating model files of target devices of an integrated circuit includes providing the target devices; providing a device target set for the target devices, wherein the device target set comprises target values of parameters of the target devices; determining a nearest known model related to the target devices, wherein the nearest known model comprises a first model file; performing a sensitivity analysis to determine sensitive parameters in the first model file; modifying the sensitive parameters in the first model file to generate a second model file; and determining a fitness value of a circuit simulated using the second model file with values of parameters in the device target set.

Abstract: A method includes selecting one of a plurality of existing transistor models for which fabrication and performance data are available, receiving first model data for a next-generation transistor based on target response data and the selected transistor model data, and simulating a response of a circuit including the next-generation transistor. The selection of the existing transistor model is based on target response data for the next-generation transistor for which fabrication and performance data are not available. The simulation is performed using the first transistor model data for the next-generation transistor. A difference between the target response and the simulated response of the next-generation transistor is calculated, and the first model data representing the next-generation transistor is stored in a computer readable storage medium if the performance data difference between the target response and the simulated response is below a threshold.

Abstract: A method for generating model files of target devices of an integrated circuit includes providing the target devices; providing a device target set for the target devices, wherein the device target set comprises target values of parameters of the target devices; determining a nearest known model related to the target devices, wherein the nearest known model comprises a first model file; performing a sensitivity analysis to determine sensitive parameters in the first model file; modifying the sensitive parameters in the first model file to generate a second model file; and determining a fitness value of a circuit simulated using the second model file with values of parameters in the device target set.

Abstract: The invention is embodied in an image data system including a lossy image compressor having an image compression ratio in excess of 10 for producing first compressed image data from an original image, the first compressed image data specifying a corresponding one of a set of predetermined images, apparatus for computing an difference between the original image and the predetermined image specified by the first compressed image data and a lossless image compressor for compressing at least the difference to produce second compressed image data.

Abstract: An architecture and design of compact neural networks is presented for the maximum-likelihood sequence estimation (MLSE) of one-dimensional signals, such as sound, in digital communications. Optimization of a concave Lyapunov function associated with a compact neural network performs a combinatorial minimization of the detection cost, and truly paralleled operations in the analog domain are achievable via the collective computational behaviors. In addition, the MLSE performance can be improved by paralleled hardware annealing, a technique for obtaining optimal or near-optimal solutions in high-speed, real-time applications. For a sequence of length n, the network of complexity and throughput rate are O(L) and n/T.sub.c, respectively, where L is the number of symbols the inference spans and T.sub.c is the convergence time. The hardware architecture as well as network models, neuron models, and methods of feeding the input to the network are addressed in terms of the probability of error.

Abstract: A motion video data system includes a compression system, including an image compressor, an image decompressor correlative to the image compressor having an input connected to an output of the image compressor, a feedback summing node having one input connected to an output of the image decompressor, a picture memory having an input connected to an output of the feedback summing node, apparatus for comparing an image stored in the picture memory with a received input image and deducing therefrom pixels having differences between the stored image and the received image and for retrieving from the picture memory a partial image including the pixels only and applying the partial image to another input of the feedback summing node, whereby to produce at the output of the feedback summing node an updated decompressed image, a subtraction node having one input connected to received the received image and another input connected to receive the partial image so as to generate a difference image, the image compressor