Abstract: The present invention provides a DP-out adapter including a decoder, a clock signal generating circuit, a DP signal generating circuit and a symbol counter value comparator. The decoder is configured to decode a USB signal to generate a plurality of packets. The clock signal generating circuit is configured to generate a clock signal. The DP signal generating circuit is configured to generate a DP signal according to the packets, and output the DP signal according to the clock signal. The symbol counter value comparator is configured to generate a first counter value according to a number of symbols corresponding to the plurality of packets, and use the clock signal to count to obtain a second counter value, and compare the first counter value and the second counter value to generate a control signal to the clock signal generating circuit to adjust a frequency of the clock signal.

Abstract: The present invention provides a DP-out adapter including a decoder, a clock signal generating circuit, a DP signal generating circuit and a symbol counter value comparator. The decoder is configured to decode a USB signal to generate a plurality of packets. The clock signal generating circuit is configured to generate a clock signal. The DP signal generating circuit is configured to generate a DP signal according to the packets, and output the DP signal according to the clock signal. The symbol counter value comparator is configured to generate a first counter value according to a number of symbols corresponding to the plurality of packets, and use the clock signal to count to obtain a second counter value, and compare the first counter value and the second counter value to generate a control signal to the clock signal generating circuit to adjust a frequency of the clock signal.

Abstract: Disclosed is a payload mapper including N mapper(s), each of which includes a controller, multiple mapping circuits, an output control circuit, and a storage circuit. The controller includes: a decoding circuit receiving a first-format signal and decoding at least a part of this signal to find out the type of a control signal relating to the first-format signal; and a conversion control circuit generating a selecting signal according to the type of the control signal to choose one of the mapping circuits. The mapping circuits receive the first-format signal and selecting signal, and the selected mapping circuit converts the first-format signal into a second-format signal according to the selecting signal. The output control circuit is coupled to the mapping circuits and outputs at least a part of the second-format signal as an effective output signal. The storage circuit temporarily stores the effective output signal and then outputs it.

Abstract: A signal receiving device adapting to a signal input mode and a signal processing method for the same are provided. The signal receiving device can determine various signal input modes, such as a differential signal or a single-ended signal, and select an appropriate signal source, such that the signal receiving device can not only receive the input signal correctly, but also adjust the received input signal to a differential signal with the same amplitude and opposite phases to make subsequent data analysis work easier.

Abstract: A signal receiving device adapting to a signal input mode and a signal processing method for the same are provided. The signal receiving device can determine various signal input modes, such as a differential signal or a single-ended signal, and select an appropriate signal source, such that the signal receiving device can not only receive the input signal correctly, but also adjust the received input signal to a differential signal with the same amplitude and opposite phases to make subsequent data analysis work easier.

Abstract: Disclosed is a payload mapper including N mapper(s), each of which includes a controller, multiple mapping circuits, an output control circuit, and a storage circuit. The controller includes: a decoding circuit receiving a first-format signal and decoding at least a part of this signal to find out the type of a control signal relating to the first-format signal; and a conversion control circuit generating a selecting signal according to the type of the control signal to choose one of the mapping circuits. The mapping circuits receive the first-format signal and selecting signal, and the selected mapping circuit converts the first-format signal into a second-format signal according to the selecting signal. The output control circuit is coupled to the mapping circuits and outputs at least a part of the second-format signal as an effective output signal. The storage circuit temporarily stores the effective output signal and then outputs it.

Abstract: The present invention provides a DP to HDMI converter, wherein the DP to HDMI converter comprises a receiving circuit, a signal converter and a transmitter. In the operations of the DP to HDMI converter, the receiving circuit is configured to receive a plurality of input signals, wherein the input signals comprise a plurality of DP signals configured to generate an image frame with variable frame rate. The signal converter is configured to receive the plurality of input signals to generate a plurality of HDMI signals, wherein the signal converter includes a synchronization signal generator for generating a vertical synchronization signal and a horizontal synchronization signal of the plurality of HDMI signals according to a portion of the input signals. The transmitter is configured to output the plurality of HDMI signals.

Abstract: Disclosed is a USB Type-C switching circuit configured for arranging a plurality of signals of a USB Type-C connector. The USB Type-C switching circuit can be used in products having DisplayPort Alternate mode, and includes a plurality of signal receivers/receivers, a plurality of series-parallel transforming circuits and a multiplexer. The signal receivers/receivers are connected to the USB Type-C connector to receive/transmit signals. The series-parallel transforming circuits are connected to the signal receivers/receivers to convert the signals between a parallel domain and a serial domain. The multiplexer is connected to the series-parallel transforming circuits to arrange the signals in the parallel domain according to a control signal.

Abstract: Disclosed is a USB Type-C switching circuit configured for arranging a plurality of signals of a USB Type-C connector. The USB Type-C switching circuit can be used in products having DisplayPort Alternate mode, and includes a plurality of signal receivers/receivers, a plurality of series-parallel transforming circuits and a multiplexer. The signal receivers/receivers are connected to the USB Type-C connector to receive/transmit signals. The series-parallel transforming circuits are connected to the signal receivers/receivers to convert the signals between a parallel domain and a serial domain. The multiplexer is connected to the series-parallel transforming circuits to arrange the signals in the parallel domain according to a control signal.

Abstract: This invention discloses circuits and methods for generating a pixel clock. The circuits utilize an image signal of a first format to generate a pixel clock, which can be utilized to generate an image signal of a second format. The circuits include a reference clock generation circuit, an image processing circuit, and a clock adjustment circuit. The reference clock generation circuit generates a reference clock. The image processing circuit processes the image signal of the first format to generate a control signal. The clock adjustment circuit, which is coupled to the reference clock generation circuit and the image signal processing circuit, generates the pixel clock according to the reference clock and the control signal. The control signal is substantially a periodic signal, whose frequency is proportional to the frequency of a synchronization signal of the image signal of the second format.

Abstract: This invention discloses circuits and methods for generating a pixel clock. The circuits utilize an image signal of a first format to generate a pixel clock, which can be utilized to generate an image signal of a second format. The circuits include a reference clock generation circuit, an image processing circuit, and a clock adjustment circuit. The reference clock generation circuit generates a reference clock. The image processing circuit processes the image signal of the first format to generate a control signal. The clock adjustment circuit, which is coupled to the reference clock generation circuit and the image signal processing circuit, generates the pixel clock according to the reference clock and the control signal. The control signal is substantially a periodic signal, whose frequency is proportional to the frequency of a synchronization signal of the image signal of the second format.

Abstract: A receiver includes; a recovery circuit for receiving an input signal, and generating a data signal and a recovery clock; a processing circuit for processing the data signal to generate a processed signal; and a synchronization determining circuit for determining a synchronization state of the recovery clock according to the processed signal and a first reference value. The data signal includes a synchronous pattern, and the first reference value corresponds to at least a portion of a value in the synchronous pattern processed by the processing circuit. A method of the receiver is also disclosed.

Abstract: A receiver includes; a recovery circuit for receiving an input signal, and generating a data signal and a recovery clock; a processing circuit for processing the data signal to generate a processed signal; and a synchronization determining circuit for determining a synchronization state of the recovery clock according to the processed signal and a first reference value. The data signal includes a synchronous pattern, and the first reference value corresponds to at least a portion of a value in the synchronous pattern processed by the processing circuit. A method of the receiver is also disclosed.