Abstract: The present invention is related to an adjustable harmonic filtering device, mainly comprising a first connecting port, a second connecting port, a harmonic filtering unit, and an adjusting unit, in which a passive network is presented between the first connecting port and the second connecting port, as well as the harmonic filtering unit is connected to the passive network. The harmonic filtering unit comprises a first inductor and a first capacitor. The adjusting unit is adjacent to the first inductor of the harmonic filtering unit, and induced electromagnetically therewith. Thus, frequency-band of the harmonic, to be filtered out by the harmonic filtering unit, may be changed, allowing for reducing loss of signal occurring in the process of transmission between the first connecting port and the second connecting port effectively.

Abstract: The present invention is related to a wireless transceiver with function of adjustment for frequency-band matching and the adjusting method therefor, mainly comprising a plurality of transmitting circuits, a plurality of receiving circuits, a frequency-band matching adjustment circuit, and a radio-frequency signal transceiving end. In this connection, the transmitting circuits and/or the receiving circuits are connected to the radio-frequency signal transceiving end via the frequency-band matching adjustment circuit. Impedance in the frequency-band matching adjustment circuit may be adjusted on the basis of the frequency-band of a RF signal, when (before) the RF signal is transmitted or received, such that high impedance or low impedance is presented in the frequency-band matching adjustment circuit with respect to the frequency-band of the received or transmitted RF signal. Thereby, loss of RF signal in reception or transmission is reduced.

Abstract: A frequency detection circuit includes a filter, a power detector and a voltage comparator. The filter receives and filters a converted signal to generate a filtered signal. The power of the filtered signal relates to a frequency of the converted signal. The power detector generates a voltage according to the power of the filtered signal. The voltage comparator compares the voltage with multiple reference voltages to generate multiple comparison results. At least one of the inductance and capacitance of an LC tank in an amplifier is adjusted according to the comparison results.

Abstract: The present invention is related to an adjustable harmonic filtering device, mainly comprising a first connecting port, a second connecting port, a harmonic filtering unit, and an adjusting unit, in which a passive network is presented between the first connecting port and the second connecting port, as well as the harmonic filtering unit is connected to the passive network. The harmonic filtering unit comprises a first inductor and a first capacitor. The adjusting unit is adjacent to the first inductor of the harmonic filtering unit, and induced electromagnetically therewith. Thus, frequency-band of the harmonic, to be filtered out by the harmonic filtering unit, may be changed, allowing for reducing loss of signal occurring in the process of transmission between the first connecting port and the second connecting port effectively.

Abstract: The present invention is related to a wireless transceiver with function of adjustment for frequency-band matching and the adjusting method therefor, mainly comprising a plurality of transmitting circuits, a plurality of receiving circuits, a frequency-band matching adjustment circuit, and a radio-frequency signal transceiving end. In this connection, the transmitting circuits and/or the receiving circuits are connected to the radio-frequency signal transceiving end via the frequency-band matching adjustment circuit. Impedance in the frequency-band matching adjustment circuit may be adjusted on the basis of the frequency-band of a RF signal, when (before) the RF signal is transmitted or received, such that high impedance or low impedance is presented in the frequency-band matching adjustment circuit with respect to the frequency-band of the received or transmitted RF signal. Thereby, loss of RF signal in reception or transmission is reduced.

Abstract: An integrated circuit (IC) and a seal ring thereof are provided. The IC includes a first seal ring. The first seal ring is disposed in the IC. The first seal ring includes at least one stagger structure. The at least one stagger structure includes at least one stagger unit. The at least one stagger unit makes staggered connection with another neighboring stagger unit.

Abstract: A frequency detection circuit includes a filter, a power detector and a voltage comparator. The filter receives and filters a converted signal to generate a filtered signal. The power of the filtered signal relates to a frequency of the converted signal. The power detector generates a voltage according to the power of the filtered signal. The voltage comparator compares the voltage with multiple reference voltages to generate multiple comparison results. At least one of the inductance and capacitance of an LC tank in an amplifier is adjusted according to the comparison results.

Abstract: A mixing unit includes a baseband signal processing unit, a radio frequency (RF) signal processing unit and a mixing unit. The baseband signal processing unit receives or generates a baseband signal. The RF signal processing unit processes or outputs a RF signal. The mixing unit is coupled to the baseband signal processing unit and the RF signal processing unit to select and operate in an up-convert mode or a down-convert mode according to a control signal. When the mixer operates in an up-convert mode, the mixing unit mixes the baseband signal with a local oscillation signal to generate the RF signal and outputs the RF signal to the RF signal processing unit. When the mixer operates in a down-convert mode, the mixing unit mixes the RF signal with the local oscillation signal to generate the baseband signal and outputs the baseband signal to the baseband signal processing unit.

Abstract: An integrated circuit (IC) and a seal ring thereof are provided. The IC includes a first seal ring. The first seal ring is disposed in the IC. The first seal ring includes at least one stagger structure. The at least one stagger structure includes at least one stagger unit. The at least one stagger unit makes staggered connection with another neighboring stagger unit.

Abstract: A steering and mixing module comprises a double balanced switch quad and a steering quad. The double balanced switch quad comprises a first output pair, and the first output pair is coupled to a first load stage. The steering quad comprises a second output pair, and the second output pair is coupled to a second load stage. The double balanced switch quad and the steering quad share an input pair.

Abstract: A physiology condition detection device comprises a physiology condition sensor, a signal converter and an RFID processor. The physiology condition sensor is configured to sense physiology condition. The signal converter is configured to convert the sensed physiology condition to digitized physiology data. The RFID processor is configured to control the operation of the physiology condition sensor and the signal converter, and report the digitized physiology data.

Abstract: A converting/steering device has a normal mode and a calibration mode. The converting/steering device includes a merged mixer/VGA and a mode controller. The merged mixer/VGA has a mixing stage and an amplifying stage. In the normal mode, the mode controller deactivates the mixing stage of the merged mixer/VGA, and the device operates as an RF VGA. In the calibration mode, the mode controller activates the mixing stage of the merged mixer/VGA and passes a local oscillator signal to the mixing stage, so that the device operates as a down-mixer.

Abstract: A steering and mixing module comprises a double balanced switch quad and a steering quad. The double balanced switch quad comprises a first output pair, and the first output pair is coupled to a first load stage. The steering quad comprises a second output pair, and the second output pair is coupled to a second load stage. The double balanced switch quad and the steering quad share an input pair.

Abstract: An input/output device comprises a bonding pad, a signal transport circuit, and a blocking unit. The signal transport circuit has a first terminal connected to the bonding pad and a second terminal connected to a core circuit of an IC product. The signal transport circuit is capable of transporting a signal either from the bonding pad to the core circuit or from the core circuit to the bonding pad. The blocking unit has a control terminal and is coupled between the bonding pad and the signal transport circuit. The control terminal is coupled to receive an enable signal. The blocking unit ties the bonding pad to a predetermined voltage level when the enable signal is de-asserted, thereby blocking the signal transport provided by the signal transport circuit. The blocking unit unties the bonding pad from the predetermined voltage level when the enable signal is asserted.

Abstract: An apparatus and method for internally calibrating a direct conversion receiver (DCR) through feeding a calibration signal via ESD protection circuitry is disclosed. The apparatus includes an internal signal generator for generating a calibration signal, a front-end input stage for receiving an RF signal at an input node, an ESD protection unit for protecting against electrostatic discharge, and a switch unit coupled to the ESD protection unit, for selectively passing a calibration signal to the front-end input stage, whereby the connection of the switch unit and the ESD protection unit means that when the DCR is operating in normal mode, the switch unit will not affect the noise performance and matching of the receiver.

Abstract: A power-to-digital converter (PDC) converting a signal power to digital code. The PDC comprises a power detector, an analog-to-digital converter (ADC), and a timing and logic control circuit. The power detector receives the signal power and generates a DC output and a first determined number of bits. The ADC is coupled to the power detector and receives and converts the DC output to a second determined number of bits. The timing control logic circuit is coupled to the power detector and the ADC and sequentially enables the power detector and the ADC. The first and second predetermined numbers of bits are respectively most significant bits (MSBs) and least significant bits (LSBs) of the digital code. The bit resolution of the digital code is the sum of the first and second numbers.

Abstract: A power-to-digital converter (PDC) converting a signal power to digital code. The PDC comprises a power detector, an analog-to-digital converter (ADC), and a timing and logic control circuit. The power detector receives the signal power and generates a DC output and a first determined number of bits. The ADC is coupled to the power detector and receives and converts the DC output to a second determined number of bits. The timing control logic circuit is coupled to the power detector and the ADC and sequentially enables the power detector and the ADC. The first and second predetermined numbers of bits are respectively most significant bits (MSBs) and least significant bits (LSBs) of the digital code. The bit resolution of the digital code is the sum of the first and second numbers.

Abstract: An apparatus and method for internally calibrating a direct conversion receiver (DCR) through feeding a calibration signal via ESD protection circuitry is disclosed. The apparatus includes an internal signal generator for generating a calibration signal, a front-end input stage for receiving an RF signal at an input node, an ESD protection unit for protecting against electrostatic discharge, and a switch unit coupled to the ESD protection unit, for selectively passing a calibration signal to the front-end input stage, whereby the connection of the switch unit and the ESD protection unit means that when the DCR is operating in normal mode, the switch unit will not affect the noise performance and matching of the receiver.

Abstract: A converting/steering device has a normal mode and a calibration mode. The converting/steering device includes a merged mixer/VGA and a mode controller. The merged mixer/VGA has a mixing stage and an amplifying stage. In the normal mode, the mode controller deactivates the mixing stage of the merged mixer/VGA, and the device operates as an RF VGA. In the calibration mode, the mode controller activates the mixing stage of the merged mixer/VGA and passes a local oscillator signal to the mixing stage, so that the device operates as a down-mixer.

Abstract: An input/output device comprises a bonding pad, a signal transport circuit, and a blocking unit. The signal transport circuit has a first terminal connected to the bonding pad and a second terminal connected to a core circuit of an IC product. The signal transport circuit is capable of transporting a signal either from the bonding pad to the core circuit or from the core circuit to the bonding pad. The blocking unit has a control terminal and is coupled between the bonding pad and the signal transport circuit. The control terminal is coupled to receive an enable signal. The blocking unit ties the bonding pad to a predetermined voltage level when the enable signal is de-asserted, thereby blocking the signal transport provided by the signal transport circuit. The blocking unit unties the bonding pad from the predetermined voltage level when the enable signal is asserted.