Patents by Inventor Bing-Lung Liao

Bing-Lung Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6459127
    Abstract: NMOS transistors for a high voltage process are protected from electrostatic discharge (ESD) by parasitic SCRs, where the two NMOS transistors and the two SCRs are designed to be in a completely symmetrical arrangement so that the currents in the components of the SCRs are completely uniform. This symmetry is achieved by adding a p+ diffusion to the source of one of the NMOS transistors. The added p+ diffusion guarantees that the resistance seen by both SCRs is identical. This insures even current distribution between both SCRs and thereby improves the high voltage characteristics of the ESD device.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: October 1, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jian-Hsing Lee, Kuo-Chio Liu, Bing-Lung Liao, Jiaw-Ren Shih
  • Publication number: 20020081783
    Abstract: NMOS transistors for a high voltage process are protected from electrostatic discharge (ESD) by parasitic SCRs, where the two NMOS transistors and the two SCRs are designed to be in a completely symmetrical arrangement so that the currents in the components of the SCRs are completely uniform. This symmetry is achieved by adding a p+ diffusion to the source of one of the NMOS transistors. The added p+ diffusion guarantees that the resistance seen by both SCRs is identical. This insures even current distribution between both SCRs and thereby improves the high voltage characteristics of the ESD device.
    Type: Application
    Filed: January 14, 2002
    Publication date: June 27, 2002
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Jian-Hsing Lee, Kuo-Chio Liu, Bing-Lung Liao, Jiaw-Ren Shih
  • Patent number: 6358781
    Abstract: NMOS transistors for a high voltage process are protected from electrostatic discharge (ESD) by parasitic SCRs, where the two NMOS transistors and the two SCRs are designed to be in a completely symmetrical arrangement so that the currents in the components of the SCRs are completely uniform. This symmetry is achieved by adding a p+ diffusion to the source of one of the NMOS transistors. The added p+ diffusion guarantees that the resistance seen by both SCRs is identical. This insures even current distribution between both SCRs and thereby improves the high voltage characteristics of the ESD device.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: March 19, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jian-Hsing Lee, Kuo-Chio Liu, Bing-Lung Liao, Jiaw-Ren Shih