Patents by Inventor Bing-Syun Yeh

Bing-Syun Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9159577
    Abstract: According to an exemplary embodiment, a method of forming a substrate pattern having an isolated region and a dense region is provided. The method includes the following operations: forming a first photoresist layer over the substrate; exposing the first photoresist layer through a first mask corresponding to the isolated region; developing the first photoresist layer to form a first pattern; forming a second photoresist layer over the substrate and the first pattern; exposing the second photoresist layer through a second mask corresponding to the substrate pattern; developing the second photoresist layer to form a second pattern; and etching the first pattern and the substrate to form the substrate pattern in the isolated region and the dense region.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chun-Yu Lin, Feng-Yuan Chiu, Bing-Syun Yeh, Yi-Jie Chen, Ying-Chou Cheng, I-Chang Shih, Ru-Gun Liu, Shih-Ming Chang
  • Publication number: 20150235857
    Abstract: According to an exemplary embodiment, a method of forming a substrate pattern having an isolated region and a dense region is provided. The method includes the following operations: forming a first photoresist layer over the substrate; exposing the first photoresist layer through a first mask corresponding to the isolated region; developing the first photoresist layer to form a first pattern; forming a second photoresist layer over the substrate and the first pattern; exposing the second photoresist layer through a second mask corresponding to the substrate pattern; developing the second photoresist layer to form a second pattern; and etching the first pattern and the substrate to form the substrate pattern in the isolated region and the dense region.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 20, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: CHUN-YU LIN, FENG-YUAN CHIU, BING-SYUN YEH, YI-JIE CHEN, YING-CHOU CHENG, I-CHANG SHIH, RU-GUN LIU, SHIH-MING CHANG
  • Patent number: 8952329
    Abstract: A method for characterizing a three-dimensional surface profile of a semiconductor workpiece is provided. In this method, the three-dimensional surface profile is imaged from a normal angle to measure widths of various surfaces in a first image. The three-dimensional surface is also imaged from a first oblique angle to re-measure the widths of the various surfaces in a second image. Based on differences in widths of corresponding surfaces for first and second images, a feature height and sidewall angle are determined for the three-dimensional profile.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Chang Shih, Yi-Jie Chen, Chia-Cheng Chang, Feng-Yuan Chiu, Ying-Chou Cheng, Chiu Hsiu Chen, Bing-Syun Yeh, Ru-Gun Liu
  • Patent number: 8381153
    Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: February 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ping Chiang, Yu-Po Tang, Ming-Hui Chih, Cheng-Kun Tsai, Wei-Long Wang, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau, Cheng-Lung Tsai, Josh J. H. Feng, Bing-Syun Yeh, Jeng-Shiun Ho, Cheng-Cheng Kuo
  • Publication number: 20120072874
    Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.
    Type: Application
    Filed: September 17, 2010
    Publication date: March 22, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ping Chiang, Yu-Po Tang, Ming-Hui Chih, Cheng-Kun Tsai, Wei-Long Wang, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau, Cheng-Lung Tsai, Josh J.H. Feng, Bing-Syun Yeh, Jeng-Shiun Ho, Cheng-Cheng Kuo
  • Publication number: 20090258302
    Abstract: A photomask including a main feature, corresponding to an integrated circuit feature, and a sub-resolution assist feature (SRAF) is provided. A first imaginary line tangential with a first edge of the main feature and a second imaginary line tangential with the second edge of the main feature define an area adjacent the main feature. A center point of the SRAF lies within this area. The SRAF may be a symmetrical feature. In an embodiment, the center point of the SRAF lies on an imaginary line extending at approximately 45-degree angle from a corner of a main feature.
    Type: Application
    Filed: April 10, 2008
    Publication date: October 15, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jeng-Shiun Ho, Jun-Hua Chen, Luke Lo, Louis Lin, Bing-Syun Yeh, Cheng-Cheng Kuo, Hua-Tai Lin