Patents by Inventor Bing-Yao Fan

Bing-Yao Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100171175
    Abstract: A semiconductor structure for high voltage/high current MOS circuits is provided, including a deep N-well (NMD), a P-well (PW) disposed within NWD, a plurality of field oxide regions (FOX), a plurality of doping regions, including both N+ regions and P+ regions, disposed within NWD and PW, a gate (G) connected to a doping region, a bulk pad (B) connected to a doping regions, a source pad (S) connected to a doping regions and a drain pad (D) connected to a doping region. The top view of the present invention shows that the regions are of non-specific shapes and overlaid in a radial manner, with doping region connected to B being encompassed by doping region connected to S, which in turn encompassed by G, encompassed by FOX, encompassed by doping region connected to D.
    Type: Application
    Filed: January 5, 2009
    Publication date: July 8, 2010
    Inventors: Bing-Yao Fan, Ming-Yi Hsieh, Tsuoe-Hsiang Liao, Maw-Hwa Chen
  • Patent number: 7696564
    Abstract: A lateral diffused metal-oxide-semiconductor field-effect transistor structure including a P substrate, an N+ buried layer, an N epitaxial layer, a P well, an N well, a drain region, a source region, and a body region is disclosed. The N+ buried layer is located between the P substrate and the N epitaxial layer, the P well contacts the N+ buried layer, the source region and the body region are located in the P well, the N well is located in the N epitaxial layer, and the drain region is located in the N well. When a high voltage is applied to the drain and the P substrate is grounded, a breakdown voltage with the P substrate is raised because of the N+ buried layer isolating the P substrate from the N epitaxial layer, so as to be able to avoid PN junction breakdown.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: April 13, 2010
    Assignee: Agamem Microelectronics Inc.
    Inventors: Tsuoe-Hsiang Liao, Bing-Yao Fan, Yi-Ju Liu