Patents by Inventor BING YOU
BING YOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12207568Abstract: Disclosed are a fabrication method for a superconducting circuit and a superconducting quantum chip. The fabrication method includes: determining, on a substrate, a first junction region located between a first electrical element and a second electrical element, and a second junction region located between a first conductive plate and a second conductive plate that are formed in advance; forming a Josephson junction in the second junction region; detect an electrical parameter of the Josephson junction, and determining whether the electrical parameter is within a target parameter range; if yes, separating the Josephson junction through cutting, and moving the Josephson junction to the first junction region; and forming a first connection structure connecting the first superconducting layer to the first electrical element and a second connection structure connecting the second superconducting layer to the second electrical element.Type: GrantFiled: May 10, 2023Date of Patent: January 21, 2025Assignee: Origin Quantum Computing Technology (Hefei) Co., LtdInventors: Liangliang Ma, Bing You, Nianci Wang, Jie Zheng, Wenshu Liu
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Publication number: 20240357945Abstract: Disclosed are a fabrication method for a superconducting circuit and a superconducting quantum chip. The fabrication method includes: determining, on a substrate, a first junction region located between a first electrical element and a second electrical element, and a second junction region located between a first conductive plate and a second conductive plate that are formed in advance; forming a Josephson junction in the second junction region; detect an electrical parameter of the Josephson junction, and determining whether the electrical parameter is within a target parameter range; if yes, separating the Josephson junction through cutting, and moving the Josephson junction to the first junction region; and forming a first connection structure connecting the first superconducting layer to the first electrical element and a second connection structure connecting the second superconducting layer to the second electrical element.Type: ApplicationFiled: May 10, 2023Publication date: October 24, 2024Applicant: ORIGIN QUANTUM COMPUTING TECHNOLOGY CO., LTD.Inventors: Liangliang MA, Bing YOU, Nianci WANG, Jie ZHENG, Wenshu LIU
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Publication number: 20240341202Abstract: A superconducting quantum circuit and a fabrication method thereof, as well as a quantum computer, belong to the field of quantum computing technology. The superconducting quantum circuit comprises a first superconducting element (21) and a second superconducting element (22) formed on a substrate (1), and a superconducting quantum interference device. The superconducting quantum interference device comprises: a bottom electrode (241) integrally connected to the second superconducting element (22); a barrier layer (242) located on the bottom electrode (241); and a top electrode (31) that is electrically connected at one end to the first superconducting element (21) and forms a partial overlapping area with the barrier layer (242) to obtain a Josephson junction at the overlapping area.Type: ApplicationFiled: January 25, 2024Publication date: October 10, 2024Applicant: Origin Quantum Computing Technology (Hefei) Co., LtdInventors: Liangliang MA, Bing YOU
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Publication number: 20240206349Abstract: A mask fabrication method, mask, Josephson junction element, and quantum chip is provided, which belong to the field of quantum information, especially the field of quantum computing. The mask fabrication method includes: providing a dielectric layer, wherein a ratio of a thickness of the dielectric layer to a line width of a target pattern to be fabricated is greater than a cutting depth-to-width ratio allowed by a patterning apparatus; determining a first sublayer and a second sublayer of the dielectric layer, wherein a ratio of a thickness of the second sublayer to the line width of the target pattern is less than or equal to the cutting depth-to-width ratio; forming the target pattern on the second sublayer and a first pattern on the first sublayer, wherein the first pattern exposes the target pattern.Type: ApplicationFiled: July 28, 2022Publication date: June 20, 2024Inventors: Yongjie ZHAO, Hui YANG, Zhipeng DAI, Liangliang MA, Bing YOU, Nianci WANG, Rui LU
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Publication number: 20230276719Abstract: Disclosed are a quantum chip and a fabrication method therefor. The quantum chip includes a base substrate on which signal transmission lines are formed; and at least one insulating substrate located on the base substrate, where a qubit and a through hole penetrating through the insulating substrate are formed on the insulating substrate, a metal piece is formed in the through hole, and two ends of the metal piece are electrically connected to the signal transmission lines and the qubit, respectively.Type: ApplicationFiled: April 27, 2023Publication date: August 31, 2023Applicant: ORIGIN QUANTUM COMPUTING TECHNOLOGY CO., LTD.Inventors: Liangliang MA, Wenshu LIU, Jie ZHENG, Nianci WANG, Bing YOU
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Patent number: 10396068Abstract: An electrostatic discharge (ESD) protection device including an ESD protection unit and a control circuit is provided. When a voltage level of a signal received by a signal input terminal reaches an ESD protection level, the ESD protection unit transmits the signal from the signal input terminal to the system voltage terminal. The control circuit controls a conduction state between the signal input terminal and the system voltage terminal through the ESD protection unit. The control circuit generates a control voltage according to the voltage level of the signal received by the signal input terminal and a system voltage level of the system voltage terminal to control the ESD protection unit, and to prevent the ESD protection unit from transmitting the signal to the system voltage terminal when the voltage level of the signal received by the signal input terminal does not reach the ESD protection level.Type: GrantFiled: March 20, 2017Date of Patent: August 27, 2019Assignee: ALi CorporationInventors: Chuan-Sheng Lee, Bing-You Gao
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Publication number: 20180090927Abstract: An integrated circuit (IC) and an operation method thereof are provided. The IC includes a first voltage rail, a second voltage rail, an electrostatic discharge (ESD) clamp circuit, a capacitor and a resistive element. A control terminal of the ESD clamp circuit receives a control signal during an ESD period, and the ESD clamp circuit provides an ESD current path between the first voltage rail and the second voltage rail. The capacitor is coupled between the control terminal and the second voltage rail. The resistive element is coupled between the control terminal and the first voltage rail. During a normal operation period, a resistance of the resistive element is a first resistance. During the ESD period, the resistance of the resistive element is a second resistance. The first resistance is smaller than the second resistance.Type: ApplicationFiled: December 16, 2016Publication date: March 29, 2018Applicant: ALi CorporationInventors: Bing-You Gao, Chuan-Sheng Lee
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Publication number: 20170324238Abstract: An electrostatic discharge (ESD) protection device including an ESD protection unit and a control circuit is provided. When a voltage level of a signal received by a signal input terminal reaches an ESD protection level, the ESD protection unit transmits the signal from the signal input terminal to the system voltage terminal. The control circuit controls a conduction state between the signal input terminal and the system voltage terminal through the ESD protection unit. The control circuit generates a control voltage according to the voltage level of the signal received by the signal input terminal and a system voltage level of the system voltage terminal to control the ESD protection unit, and to prevent the ESD protection unit from transmitting the signal to the system voltage terminal when the voltage level of the signal received by the signal input terminal does not reach the ESD protection level.Type: ApplicationFiled: March 20, 2017Publication date: November 9, 2017Applicant: ALi CorporationInventors: Chuan-Sheng Lee, Bing-You Gao
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Patent number: 9136657Abstract: An annular signal feed module is composed of a jack and a plug. The annular signal feed module includes the signal feed function of the traditional headphone. Besides, there is no jack hole in construction so that the moisture, water and dust intrusion are incapable to corrode and immerse the contacts and internal circuit parts, therefore, prolong the durability of the headphone signal feed device and the related electronic apparatuses such as televisions, stereos, cell phones and so forth. The present annular signal feed module is designed to integrate the features pertaining to no jack hole in construction of previous model patent certification no. M419356, and simplify the structural complexity, more than those, less modifications from traditional molds make it easier and convenient to be manufactured than product of patent no. M419356.Type: GrantFiled: August 7, 2013Date of Patent: September 15, 2015Inventor: Bing You
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Patent number: 8801224Abstract: The present invention provides an LED illumination device including a base, at least one flexible circuit board and a plurality of LEDs. The at least one flexible circuit board is used for covering the base. The LEDs are mounted on the flexible circuit board. The present invention utilizes a flexible circuit board that can conform to the base having a 360 degree curved surface and a 3D solid structure to efficiently change the viewing angle of the LEDs so as to provide 360 degree viewing angle. Furthermore, a single flexible circuit board can be utilized to cover the base to provide a 360 degree viewing angle. Therefore, the LED illumination device of the present invention can reduce manufacturing cost and simplify the manufacturing process.Type: GrantFiled: June 9, 2011Date of Patent: August 12, 2014Assignee: Parlux Optoelectronics Co., Ltd.Inventors: Tang-Chieh Huang, Yu-Tang Yen, Ching-Hao Chang, Bing-You Weng, Sunao Hsu, Yao-Wen Liu
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Publication number: 20140051306Abstract: An annular signal feed module is composed of a jack and a plug. The annular signal feed module includes the signal feed function of the traditional headphone. Besides, there is no jack hole in construction so that the moisture, water and dust intrusion are incapable to corrode and immerse the contacts and internal circuit parts, therefore, prolong the durability of the headphone signal feed device and the related electronic apparatuses such as televisions, stereos, cell phones and so forth. The present annular signal feed module is designed to integrate the features pertaining to no jack hole in construction of previous model patent certification no. M419356, and simplify the structural complexity, more than those, less modifications from traditional molds make it easier and convenient to be manufactured than product of patent no. M419356.Type: ApplicationFiled: August 7, 2013Publication date: February 20, 2014Inventor: BING YOU
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Publication number: 20120106153Abstract: The present invention provides an LED illumination device including a base, at least one flexible circuit board and a plurality of LEDs. The at least one flexible circuit board is used for covering the base. The LEDs are mounted on the flexible circuit board. The present invention utilizes a flexible circuit board that can conform to the base having a 360 degree curved surface and a 3D solid structure to efficiently change the viewing angle of the LEDs so as to provide 360 degree viewing angle. Furthermore, a single flexible circuit board can be utilized to cover the base to provide a 360 degree viewing angle. Therefore, the LED illumination device of the present invention can reduce manufacturing cost and simplify the manufacturing process.Type: ApplicationFiled: June 9, 2011Publication date: May 3, 2012Applicant: PARLUX OPTOELECTRONICS CO, LTD.Inventors: TANG-CHIEH HUANG, Yu-Tang Yen, Ching-Hao Chang, Bing-You Weng, Sunao Hsu, Yao-Wen Liu