Abstract: A gate fabrication method of an UMOSFET and a trench gate structure formed thereof are provided, comprising providing a transistor structure and a lithography process is employed to define a trench region. A gate oxide layer is deposited along the trench and two polysilicon sidewalls having a spacing there in between are formed afterwards. A wet etching is used to remove the gate oxide layer underneath the polysilicon sidewalls such that a vacancy is formed at the trench bottom. By oxidizing the polysilicon sidewalls, a thick oxide layer is formed, enfolding periphery of the polysilicon sidewalls and filling the vacancy. The spacing can be alternatively retained between the polysilicon sidewalls covered with the thick oxide layer, such that the trench can be alternatively filled. The present invention is effective in increasing oxide thickness of the gate bottom, reducing the trench corner curvature as well as the feedback capacitance.

Abstract: A three-dimensional source contact structure and its fabrication process method thereof are applicable to a power device, in which an inter-layer dielectric is deposited thereon. A lithography process is applied for forming a first and second dielectric layer. A spacer is respectively provided on opposite sidewalls of the first and second dielectric layer. And a shallow trench process is sequentially performed along the opposite surfaces of the spacers. The spacers are removed after the shallow trench process is complete for exposing a first and a second metal-source surface contact region. The present invention achieves in increasing horizontal surface contact and longitudinal vertical contact when depositing a source contact metal, thereby a step-like three-dimensional source contact structure can be formed. By employing the present invention, it enhances to reduce cell pitch effectively and can be widely applied to various power devices having MOSFET structure thereof.

Abstract: A process method for fabricating a three-dimensional source contact structure is provided, which is applicable to form a step-like three-dimensional source contact structure in a MOSFET of a power device. The proposed method sequentially adopts a lithography process and a shallow trench process to form a metal contact window. And a lateral etching process, or spacers which will be removed eventually, can be alternatively provided for increasing horizontal surface contact when depositing a source contact metal. Meanwhile, a longitudinal surface exposed by the shallow trench process is also beneficial to increase vertical contact when depositing the source contact metal. As a result, a step-like three-dimensional source contact structure can be formed by employing the present invention. It is believed that the present invention achieves in reducing cell pitch effectively and can be widely applied to various power devices having MOSFET structure thereof.

Abstract: A three-dimensional source contact structure and fabrication process method thereof are provided. A lithography process and shallow trench process are sequentially performed to form a metal contact window in a power device. A source heavily doped area is divided by the metal contact window into a first and second heavily doped region. A lateral etching process is applied to an inter-layer dielectric to form a first and a second dielectric layer, each of which is in a trapezoid shape. Meanwhile, a first and a second metal-source surface contact regions are exposed. A longitudinal surface exposed by the shallow trench process is beneficial to increase vertical contact when depositing a source contact metal, thereby a step-like three-dimensional source contact structure can be formed. The present invention achieves in reducing cell pitch effectively and can be widely applied to various power devices having MOSFET structure thereof.

Abstract: A source-body self-aligned method of a VDMOSFET is provided. A pad layer and an unoxidized material layer are sequentially formed on an epitaxial layer on a semiconductor substrate. A lithography process is then carried out for patterning. Later, a thermal oxidation process is employed such that the unoxidized material layer is oxidized to form oxidation layers. Then, a source ion implantation process is performed, and a wet etching is used to remove the oxidation layers before successively employing a body ion implantation process. By using the process method disclosed in the present invention, it achieves to form the source region and the body region which are self-aligned. Meanwhile, since process complexity of the invention is relatively low, process uniformity and process cost can be optimally controlled. In addition, the invention achieves to reduce channel length and on-resistance, thereby enhancing the reliability effectively.

Abstract: A method for reducing parasitic junction field effect transistor resistance, applicable to a high power device having a semiconductor substrate layer, is provided, including providing a plurality of hard masks on a top surface of the semiconductor substrate layer. Each hard mask has a bottom plane and a tilt sidewall such that an acute angle is formed there in between. A body ion implantation process is subsequently performed, so a body region is formed between two adjacent hard masks. The body region has an upper and a lower surface. A width of the upper surface is greater than that of the lower surface. Therefore, the present invention achieves to control a parasitic JFET region characterized by having a wider bottom and a narrower top, thereby reducing its resistance thereof. Meanwhile, since a bottom angle of the body region is increased, breakdown voltage of the device is increased as well.

Abstract: A method for stabilizing breakdown voltages of floating guard ring, applicable to a high power device, is provided. The high power device has a semiconductor substrate layer, and at least one floating guard ring is formed at its termination. The method includes sequentially providing a pad oxide layer and barrier layer on an upper surface of the high power device to expose the floating guard ring, and then performing an ion implantation step. After removing the pad oxide layer and barrier layer, grow a field oxide layer, such that a defect layer is formed underneath. By employing the formed defect layer, the present invention achieves to control an interface potential level between the field oxide layer and the semiconductor substrate layer fixed at a certain potential value, without being affected by charges in the oxide layer or metal across over it, thereby stabilizing breakdown voltages of floating guard ring.

Abstract: A method for increasing an oxide thickness at trench corner of an UMOSFET is provided, comprising providing an N-type substrate, and forming an N-type drift region, N-type and P-type heavily doped regions and P-type body therein. A trench is defined through lithography, and a pad oxide is formed along the trench through oxidation or deposition process. An oxidation barrier is formed upon the pad oxide. A thermal oxidation process is employed, so a corner oxide is effectively formed at the trench corner. After removing the pad oxide and oxidation barrier, various back-end processes are carried out to complete the transistor structure. The invention is aimed to increase oxide thickness near the trench bottom, and can be applied to high voltage devices, such as SiC. The conventional electric field crowding effect occurring at the trench corner is greatly solved, thus increasing breakdown voltages thereof.

Abstract: A structure of trench transistors includes the following elements. A substrate serves as a drain of the structure of trench transistors. An epitaxial layer is disposed on the substrate. A plurality of trenches are disposed in the epitaxial layer. A plurality of gate insulator layers are respectively disposed on the inner surfaces of the trenches. A plurality of gates are respectively disposed on the gate insulator layers. A plurality of first base regions are respectively disposed in the epitaxial layer between the adjacent trenches, and have a first depth from the top surface of the epitaxial layer. A plurality of second base regions are respectively disposed in the epitaxial layer adjacent to the sidewalls of the trenches, and each has a second depth from the bottom surface of the first base region. A plurality of sources are respectively disposed in the first base region beside the sidewalls of the trenches.

Abstract: A method for increasing an oxide thickness at trench corner of an UMOSFET is provided, comprising providing an N-type substrate, and forming an N-type drift region, N-type and P-type heavily doped regions and P-type body therein. A trench is defined through lithography, and a pad oxide is formed along the trench through oxidation or deposition process. An oxidation barrier is formed upon the pad oxide. A thermal oxidation process is employed, so a corner oxide is effectively formed at the trench corner. After removing the pad oxide and oxidation barrier, various back-end processes are carried out to complete the transistor structure. The invention is aimed to increase oxide thickness near the trench bottom, and can be applied to high voltage devices, such as SiC.

Abstract: A structure of trench transistors includes the following elements. A substrate serves as a drain of the structure of trench transistors. An epitaxial layer is disposed on the substrate. A plurality of trenches are disposed in the epitaxial layer. A plurality of gate insulator layers are respectively disposed on the inner surfaces of the trenches. A plurality of gates are respectively disposed on the gate insulator layers. A plurality of first base regions are respectively disposed in the epitaxial layer between the adjacent trenches, and have a first depth from the top surface of the epitaxial layer. A plurality of second base regions are respectively disposed in the epitaxial layer adjacent to the sidewalls of the trenches, and each has a second depth from the bottom surface of the first base region. A plurality of sources are respectively disposed in the first base region beside the sidewalls of the trenches.

Abstract: An enhanced tunnel field effect transistor includes a substrate, a layer of P-I-N structure, a hetero-material layer, a gate dielectric layer, a gate structure and a spacer, in which the layer of P-I-N structure is disposed on the substrate, the hetero-material layer is disposed on portion of the layer of P-I-N structure, the gate dielectric layer is disposed on the hetero-material layer, the gate structure is disposed the gate dielectric layer and a spacer is disposed on a sidewall of the hetero-material layer, the gate dielectric layer, and the gate structure. The hetero-material layer can increase the tunneling efficiency of the enhanced tunnel field effect transistor to increase the conductor current to improve the enhanced tunnel field effect transistor performance.

Abstract: A method of fabricating an MOS device is described. A substrate doped a first type dopant is provided as a drain. A first type epitaxial layer is formed on the substrate and is patterned with a trench to form several islands. A gate dielectric layer is then formed on the surface of the trench, and a gate is formed in the trench covering the gate dielectric layer. A second type dopant is doped into the islands with the doping concentration decreasing gradually from the bottom to the top of the islands. Afterwards, a source is formed at the top of the islands. Accordingly, the doping concentration in the islands decreases gradually from the drain to the source with the highest doping concentration near the drain. Therefore, the width of the depletion region can be reduced, and the length of the device channel can be reduced for lowering channel resistance and gate capacitance.

Abstract: A method of fabricating an MOS device is described. A substrate doped a first type dopant is provided as a drain. A first type epitaxial layer is formed on the substrate and is patterned with a trench to form several islands. A gate dielectric layer is than formed on the surface of the trench, and a gate is formed in the trench covering the gate dielectric layer. A second type dopant is doped into the islandswith the doping concentration decreasing gradually from the bottom to the top of the islands. Afterwards, a source is formed at the top of the islands. Accordingly, the doping concentration in the islands decreases gradually from the drain to the sourcewith the highest doping concentration near the drain. Therefore, the width of the depletion region can be reduced, and the length of the device channel can be reduced for lowering channel resistance and gate capacitance.

Abstract: A method of fabricating an MOS device is described. A substrate doped a first type dopant is provided as a drain. A first type epitaxial layer is formed on the substrate and is patterned with a trench to form several islands. A gate dielectric layer is than formed on the surface of the trench, and a gate is formed in the trench covering the gate dielectric layer. A second type dopant is doped into the islands with the doping concentration decreasing gradually from the bottom to the top of the islands. Afterwards, a source is formed at the top of the islands. Accordingly, the doping concentration in the islands decreases gradually from the drain to the source with the highest doping concentration near the drain. Therefore, the width of the depletion region can be reduced, and the length of the device channel can be reduced for lowering channel resistance and gate capacitance.

Abstract: A method of fabricating an MOS device is described. A substrate doped a first type dopant is provided as a drain. A first type epitaxial layer is formed on the substrate and is patterned with a trench to form several islands. A gate dielectric layer is than formed on the surface of the trench, and a gate is formed in the trench covering the gate dielectric layer. A second type dopant is doped into the islands with the doping concentration decreasing gradually from the bottom to the top of the islands. Afterwards, a source is formed at the top of the islands. Accordingly, the doping concentration in the islands decreases gradually from the drain to the source with the highest doping concentration near the drain. Therefore, the width of the depletion region can be reduced, and the length of the device channel can be reduced for lowering channel resistance and gate capacitance.

Abstract: A method of fabricating an MOS device is described. A substrate doped a first type dopant is provided as a drain. A first type epitaxial layer is formed on the substrate and is patterned with a trench to form several islands. A gate dielectric layer is than formed on the surface of the trench, and a gate is formed in the trench covering the gate dielectric layer. A second type dopant is doped into the islandswith the doping concentration decreasing gradually from the bottom to the top of the islands. Afterwards, a source is formed at the top of the islands. Accordingly, the doping concentration in the islands decreases gradually from the drain to the sourcewith the highest doping concentration near the drain. Therefore, the width of the depletion region can be reduced, and the length of the device channel can be reduced for lowering channel resistance and gate capacitance.

Abstract: The present invention proposes a nano-scale high-performance SOI MOSFET device and a process for manufacturing the same. The device is characterized by comprising: a metal oxide semiconductor, formed on the SOI substrate; a silicide layer (05), wherein a gate consists of a single full silicide gate (10), a high-K dielectric layer (08) and a part for work function modification (09); and source/drain (6) are complete through a silicide reaction and has a modified Schottky junction.

Abstract: The present invention discloses an electrode structure of a light emitted diode and manufacturing method of the electrodes. After formed a pn junction of a light emitted diode on a substrate, a layer of SiO2 is deposited on the periphery of the die of the LED near the scribe line of the wafer, then a transparent conductive layer is deposited blanketly, then a layer of gold or AuGe etc. is formed with an opening on the center of the die. After forming alloy with the semiconductor by heat treatment to form ohmic contact, a strip of aluminum (Al) is formed on one side of the die on the front side for wire bonding and to be the positive electrode of the LED. The negative electrode is formed on the substrate by metal contact.

Abstract: The present invention disclosed a method and apparatus for removing a SiC or a low k dielectric film, wherein the SiC or low k dielectric film is deposited on a substrate. The method comprising: Process the low k dielectric film or SiC film with high temperature oxidation, such as wet oxidation or dry oxidation, to transform the film into an oxide film layer, then remove the oxide film layer by wet etching. The present invention also disclosed an apparatus to perform the process, comprising: a high temperature processing unit such as a high temperature furnace, and a wet etching unit such as a wet bench or a single wafer spin etching processor. These units may form as a single apparatus, a cluster tool or separate tools.