Patents by Inventor Bing-Yue Tsui

Bing-Yue Tsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8853824
    Abstract: An enhanced tunnel field effect transistor includes a substrate, a layer of P-I-N structure, a hetero-material layer, a gate dielectric layer, a gate structure and a spacer, in which the layer of P-I-N structure is disposed on the substrate, the hetero-material layer is disposed on portion of the layer of P-I-N structure, the gate dielectric layer is disposed on the hetero-material layer, the gate structure is disposed the gate dielectric layer and a spacer is disposed on a sidewall of the hetero-material layer, the gate dielectric layer, and the gate structure. The hetero-material layer can increase the tunneling efficiency of the enhanced tunnel field effect transistor to increase the conductor current to improve the enhanced tunnel field effect transistor performance.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: October 7, 2014
    Assignee: National Chiao Tung University
    Inventors: Pei-Yu Wang, Bing-Yue Tsui
  • Patent number: 7517759
    Abstract: A method of fabricating an MOS device is described. A substrate doped a first type dopant is provided as a drain. A first type epitaxial layer is formed on the substrate and is patterned with a trench to form several islands. A gate dielectric layer is then formed on the surface of the trench, and a gate is formed in the trench covering the gate dielectric layer. A second type dopant is doped into the islands with the doping concentration decreasing gradually from the bottom to the top of the islands. Afterwards, a source is formed at the top of the islands. Accordingly, the doping concentration in the islands decreases gradually from the drain to the source with the highest doping concentration near the drain. Therefore, the width of the depletion region can be reduced, and the length of the device channel can be reduced for lowering channel resistance and gate capacitance.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: April 14, 2009
    Assignee: Episil Technologies Inc.
    Inventor: Bing-Yue Tsui
  • Patent number: 7391079
    Abstract: A method of fabricating an MOS device is described. A substrate doped a first type dopant is provided as a drain. A first type epitaxial layer is formed on the substrate and is patterned with a trench to form several islands. A gate dielectric layer is than formed on the surface of the trench, and a gate is formed in the trench covering the gate dielectric layer. A second type dopant is doped into the islandswith the doping concentration decreasing gradually from the bottom to the top of the islands. Afterwards, a source is formed at the top of the islands. Accordingly, the doping concentration in the islands decreases gradually from the drain to the sourcewith the highest doping concentration near the drain. Therefore, the width of the depletion region can be reduced, and the length of the device channel can be reduced for lowering channel resistance and gate capacitance.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: June 24, 2008
    Assignee: Episil Technologies Inc.
    Inventor: Bing-Yue Tsui
  • Publication number: 20080009118
    Abstract: A method of fabricating an MOS device is described. A substrate doped a first type dopant is provided as a drain. A first type epitaxial layer is formed on the substrate and is patterned with a trench to form several islands. A gate dielectric layer is than formed on the surface of the trench, and a gate is formed in the trench covering the gate dielectric layer. A second type dopant is doped into the islands with the doping concentration decreasing gradually from the bottom to the top of the islands. Afterwards, a source is formed at the top of the islands. Accordingly, the doping concentration in the islands decreases gradually from the drain to the source with the highest doping concentration near the drain. Therefore, the width of the depletion region can be reduced, and the length of the device channel can be reduced for lowering channel resistance and gate capacitance.
    Type: Application
    Filed: September 25, 2007
    Publication date: January 10, 2008
    Inventor: BING-YUE TSUI
  • Patent number: 7294550
    Abstract: A method of fabricating an MOS device is described. A substrate doped a first type dopant is provided as a drain. A first type epitaxial layer is formed on the substrate and is patterned with a trench to form several islands. A gate dielectric layer is than formed on the surface of the trench, and a gate is formed in the trench covering the gate dielectric layer. A second type dopant is doped into the islands with the doping concentration decreasing gradually from the bottom to the top of the islands. Afterwards, a source is formed at the top of the islands. Accordingly, the doping concentration in the islands decreases gradually from the drain to the source with the highest doping concentration near the drain. Therefore, the width of the depletion region can be reduced, and the length of the device channel can be reduced for lowering channel resistance and gate capacitance.
    Type: Grant
    Filed: September 14, 2004
    Date of Patent: November 13, 2007
    Assignee: Episil Technologies Inc.
    Inventor: Bing-Yue Tsui
  • Publication number: 20070080396
    Abstract: A method of fabricating an MOS device is described. A substrate doped a first type dopant is provided as a drain. A first type epitaxial layer is formed on the substrate and is patterned with a trench to form several islands. A gate dielectric layer is than formed on the surface of the trench, and a gate is formed in the trench covering the gate dielectric layer. A second type dopant is doped into the islandswith the doping concentration decreasing gradually from the bottom to the top of the islands. Afterwards, a source is formed at the top of the islands. Accordingly, the doping concentration in the islands decreases gradually from the drain to the sourcewith the highest doping concentration near the drain. Therefore, the width of the depletion region can be reduced, and the length of the device channel can be reduced for lowering channel resistance and gate capacitance.
    Type: Application
    Filed: October 5, 2006
    Publication date: April 12, 2007
    Inventor: BING-YUE TSUI
  • Publication number: 20060255405
    Abstract: The present invention proposes a nano-scale high-performance SOI MOSFET device and a process for manufacturing the same. The device is characterized by comprising: a metal oxide semiconductor, formed on the SOI substrate; a silicide layer (05), wherein a gate consists of a single full silicide gate (10), a high-K dielectric layer (08) and a part for work function modification (09); and source/drain (6) are complete through a silicide reaction and has a modified Schottky junction.
    Type: Application
    Filed: September 21, 2005
    Publication date: November 16, 2006
    Applicant: National Chiao Tung University
    Inventors: Bing-Yue Tsui, Chia-Pin Lin
  • Patent number: 7115526
    Abstract: The present invention discloses an electrode structure of a light emitted diode and manufacturing method of the electrodes. After formed a pn junction of a light emitted diode on a substrate, a layer of SiO2 is deposited on the periphery of the die of the LED near the scribe line of the wafer, then a transparent conductive layer is deposited blanketly, then a layer of gold or AuGe etc. is formed with an opening on the center of the die. After forming alloy with the semiconductor by heat treatment to form ohmic contact, a strip of aluminum (Al) is formed on one side of the die on the front side for wire bonding and to be the positive electrode of the LED. The negative electrode is formed on the substrate by metal contact.
    Type: Grant
    Filed: March 18, 2002
    Date of Patent: October 3, 2006
    Assignee: Grand Plastic Technology Corporation Taiwan
    Inventors: Hsieh Yue Ho, Chih-Cheng Wang, Hsiao Shih-Yi, Kang Tsung-Kuei, Bing-Yue Tsui, Chih-Feng Huang, Jann-Shyang Liang, Ming-Huan Tsai, Hun-Jan Tao, Baw-ching Perng
  • Publication number: 20060016786
    Abstract: The present invention disclosed a method and apparatus for removing a SiC or a low k dielectric film, wherein the SiC or low k dielectric film is deposited on a substrate. The method comprising: Process the low k dielectric film or SiC film with high temperature oxidation, such as wet oxidation or dry oxidation, to transform the film into an oxide film layer, then remove the oxide film layer by wet etching. The present invention also disclosed an apparatus to perform the process, comprising: a high temperature processing unit such as a high temperature furnace, and a wet etching unit such as a wet bench or a single wafer spin etching processor. These units may form as a single apparatus, a cluster tool or separate tools.
    Type: Application
    Filed: July 26, 2004
    Publication date: January 26, 2006
    Inventors: Bing-Yue Tsui, Kuo-Lung Fang, Yuan-Hsin Li, Chih-Hung Wu
  • Publication number: 20050133833
    Abstract: A method of fabricating an MOS device is described. A substrate doped a first type dopant is provided as a drain. A first type epitaxial layer is formed on the substrate and is patterned with a trench to form several islands. A gate dielectric layer is than formed on the surface of the trench, and a gate is formed in the trench covering the gate dielectric layer. A second type dopant is doped into the islands with the doping concentration decreasing gradually from the bottom to the top of the islands. Afterwards, a source is formed at the top of the islands. Accordingly, the doping concentration in the islands decreases gradually from the drain to the source with the highest doping concentration near the drain. Therefore, the width of the depletion region can be reduced, and the length of the device channel can be reduced for lowering channel resistance and gate capacitance.
    Type: Application
    Filed: September 14, 2004
    Publication date: June 23, 2005
    Inventor: Bing-Yue Tsui
  • Patent number: 6835611
    Abstract: The present invention provides a structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which comprises a SOI (Silicon-On-Insulator) device, a MOS (Metal Oxide Semiconductor) formed on said SOI device, and a metal-silicide layer. Said SOI device includes a substrate, an insulation layer formed on said substrate, and a silicon layer formed on said insulation layer, and the MOS is formed on said SOI device. The metal-silicide layer is formed in accordance with a metal aligned process by a metal layer being deposited on said SOI device and on said MOS for reacting with said silicon layer, and an implant-to-silicide process is employed to form a high-density source region and a high-density drain region for modifying Schottky Barrier and diminishing Carrier Injection Resistance.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: December 28, 2004
    Assignee: National Chiao Tung University
    Inventors: Bing-Yue Tsui, Chih-Feng Huang
  • Patent number: 6759305
    Abstract: A method for increasing the capacity of an integrated circuit device. The method includes the steps of defining a catalyst area on a substrate, forming a nanotube, nanowire, or nanobelt on the catalyst area, forming a first dielectric layer on the nanotube, nanowire, or nanobelt and the substrate, and forming an electrode layer on the first dielectric layer. According to above method, the capacity is substantially increased without extending the original bottom area of the capacitor electrode by using the surface area of the nanotube, nanowire, or nanobelt as the area of the capacitor electrode.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: July 6, 2004
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Tao Lee, Cheng-Chung Lee, Bing-Yue Tsui
  • Publication number: 20040080000
    Abstract: The present invention provides an alloy system as metal gate material of MOSFET devices that can solve the issue of work function incompatibility of metal gate and then can achieve low threshold voltage of surface channel MOSFETs effectively to satisfy the requirement of low voltage and high performance operation. To achieve this purpose, a chemically inert and thermally stable element, platinum (Pt), with high work function is selected as the basic component, which is doped with low work function element, such as tantalum (Ta), or titanium (Ti) to various atomic ratios. The work function can be adjusted to arbitrary value depends on the atomic ratio of element.
    Type: Application
    Filed: October 23, 2002
    Publication date: April 29, 2004
    Applicant: National Chiao Tung University
    Inventors: Bing-Yue Tsui, Chih-Feng Huang
  • Publication number: 20030189226
    Abstract: The present invention provides a structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which comprises a SOI (Silicon-On-Insulator) device, a MOS (Metal Oxide Semiconductor) formed on said SOI device, and a metal-silicide layer. Said SOI device includes a substrate, an insulation layer formed on said substrate, and a silicon layer formed on said insulation layer, and the MOS is formed on said SOI device. The metal-silicide layer is formed in accordance with a metal aligned process by a metal layer being deposited on said SOI device and on said MOS for reacting with said silicon layer, and an implant-to-silicide process is employed to form a high-density source region and a high-density drain region for modifying Schottky Barrier and diminishing Carrier Injection Resistance.
    Type: Application
    Filed: April 4, 2002
    Publication date: October 9, 2003
    Applicant: National Chiao Tung University
    Inventors: Bing-Yue Tsui, Chih-Feng Huang
  • Publication number: 20030148625
    Abstract: The present invention discloses an electrode structure of a light emitted diode and manufacturing method of the electrodes. After formed a pn junction of a light emitted diode on a substrate, a layer of SiO2 is deposited on the periphery of the die of the LED near the scribe line of the wafer, then a transparent conductive layer is deposited blanketly, then a layer of gold or AuGe etc. is formed with an opening on the center of the die. After forming alloy with the semiconductor by heat treatment to form ohmic contact, a strip of aluminum (Al) is formed on one side of the die on the front side for wire bonding and to be the positive electrode of the LED. The negative electrode is formed on the substrate by metal contact.
    Type: Application
    Filed: March 18, 2002
    Publication date: August 7, 2003
    Inventors: Hsieh Yue Ho, Chih-Cheng Wang, Hsiao Shih-Yi, Kang Tsung-Kuei, Bing-Yue Tsui, Chih-Feng Huang, Jann-Shyang Liang, Ming-Huan Tsai, Hun-Jan Tao, Baw-Ching Perng
  • Publication number: 20030100189
    Abstract: A method for increasing the capacity of an integrated circuit device. The method includes the steps of defining a catalyst area on a substrate, forming a nanotube, nanowire, or nanobelt on the catalyst area, forming a first dielectric layer on the nanotube, nanowire, or nanobelt and the substrate, and forming an electrode layer on the first dielectric layer. According to above method, the capacity is substantially increased without extending the original bottom area of the capacitor electrode by using the surface area of the nanotube, nanowire, or nanobelt as the area of the capacitor electrode.
    Type: Application
    Filed: April 16, 2002
    Publication date: May 29, 2003
    Inventors: Chun-Tao Lee, Cheng-Chung Lee, Bing-Yue Tsui
  • Patent number: 6566752
    Abstract: A bonding pad that has low parasitic capacitance and that transmits little or no stress to the underlying metal layer during bonding, along with a process for manufacturing it, is described. A key feature of this structure is that the damascene wiring directly below the bonding pad has been limited to its outer edges, that is it is formed in the shape of a hollow square. This limits overlap by the aluminum pad of the damascene wiring to the via hole area only. After a passivation layer, including suitable diffusion barriers, has been laid over the structure, it is over-filled with a suitable soft metal (typically copper or one of its alloys) and then planarized in the usual way. A via hole for communicating with the damascene wiring is then formed. This via can take the shape of a somewhat smaller hollow square or it can be formed from a series of individual vias arranged in the shape of a broken hollow square.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: May 20, 2003
    Assignee: Industrial Technology Research Institute
    Inventors: Chin Chiu Hsia, Bing-Yue Tsui, Tsung-Ju Yang, Tsung Yao Chu
  • Patent number: 6489204
    Abstract: Using current technology, the only way to further increase device density is to decrease device pitch. The present invention achieves this by introducing a sidewall doping process that effectively reduces the source width, and hence the pitch. This sidewall doping process also eliminates the need for a source implantation mask while the sidewall spacer facilitates silicide formation at the source, the P body contact, and the polysilicon gate simultaneously. Since the source and P body are fully covered by silicide, the contact number and contact resistance can be minimized. The silicided polysilicon gate has a low sheet resistance of about 4-6 ohm/square, resulting in a higher operating frequency.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: December 3, 2002
    Assignee: Episil Technologies, Inc.
    Inventor: Bing-Yue Tsui
  • Publication number: 20020149115
    Abstract: A bonding pad that has low parasitic capacitance and that transmits little or no stress to the underlying metal layer during bonding, along with a process for manufacturing it, is described. A key feature of this structure is that the damascene wiring directly below the bonding pad has been limited to its outer edges, that is it is formed in the shape of a hollow square. This limits overlap by the aluminum pad of the damascene wiring to the via hole area only. After a passivation layer, including suitable diffusion barriers, has been laid over the structure, it is over-filled with a suitable soft metal (typically copper or one of its alloys) and then planarized in the usual way. A via hole for communicating with the damascene wiring is then formed. This via can take the shape of a somewhat smaller hollow square or it can be formed from a series of individual vias arranged in the shape of a broken hollow square.
    Type: Application
    Filed: June 12, 2002
    Publication date: October 17, 2002
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chin Chiu Hsia, Bing-Yue Tsui, Tsung-Ju Yang, Tsung Yao Chu
  • Patent number: 6426555
    Abstract: A bonding pad that has low parasitic capacitance and that transmits little or no stress to the underlying metal layer during bonding, along with a process for manufacturing it, is described. A key feature of this structure is that the damascene wiring directly below the bonding pad has been limited to its outer edges, that is it is formed in the shape of a hollow square. This limits overlap by the aluminum pad of the damascene wiring to the via hole area only. After a passivation layer, including suitable diffusion barriers, has been laid over the structure, it is over-filled with a suitable soft metal (typically copper or one of its alloys) and then planarized in the usual way. A via hole for communicating with the damascene wiring is then formed. This via can take the shape of a somewhat smaller hollow square or it can be formed from a series of individual vias arranged in the shape of a broken hollow square.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: July 30, 2002
    Assignee: Industrial Technology Research Institute
    Inventors: Chin Chiu Hsia, Bing-Yue Tsui, Tsung-Ju Yang, Tsung Yao Chu