Abstract: A system and method for protecting register write operations, especially register write operations performed in a USB PHY. A USB transmitter/receiver, operable to receive a register write command from a USB LINK device, may monitor the write sequence initiated by the register write command to determine if/when the register write sequence has been interrupted. In monitoring the register write sequence, the USB transmitter/receiver is operable to discard the register write command if a DIR signal issued by the USB transmitter/receiver is asserted during the register write sequence and/or if an STP signal received by the USB transmitter/receiver is asserted during the register write sequence, where STP may be part of a normal register write operation. The USB transmitter/receiver is further operable to allow the register write sequence to complete if the STP signal and the DIR signal are not asserted during a predetermined period of the register write sequence.

Abstract: A system and method for protecting register write operations, especially register write operations performed in a USB PHY. A USB transmitter/receiver, operable to receive a register write command from a USB LINK device, may monitor the write sequence initiated by the register write command to determine if/when the register write sequence has been interrupted. In monitoring the register write sequence, the USB transmitter/receiver is operable to discard the register write command if a DIR signal issued by the USB transmitter/receiver is asserted during the register write sequence and/or if an STP signal received by the USB transmitter/receiver is asserted during the register write sequence, where STP may be part of a normal register write operation. The USB transmitter/receiver is further operable to allow the register write sequence to complete if the STP signal and the DIR signal are not asserted during a predetermined period of the register write sequence.

Abstract: An over frequency detection circuit which is based on the concept of a critical path in a design to protect an IC chip from running at a rate which will produce unpredictable results. The over frequency detection circuit will compare the output of a critical path generation circuit with that of a known path generation circuit. The known path generation circuit must have a delay which is guaranteed to be much shorter than the delay of the critical path generation circuit. If the output of the critical path generation circuit is not the same as the output of the known path generation circuit, then the critical path generation circuit has begun to fail and the IC chip should be disabled.