Abstract: A time synchronization method includes: after sending a synchronization message to the opposite end, sending a following message where an ending time for sending the synchronization message is recorded; receiving a delay request message sent by the opposite end, and sending a delay response message where the initial time for receiving the delay request message is recorded; receiving the synchronization message and the following message, and recording the initial time for receiving the synchronization message and the ending time recorded in the following message for sending the synchronization message; sending a delay request message, and recording an ending time for sending the delay request message; receiving a delay response message, and recording an initial time recorded in the delay response message for the opposite end to receive the delay request message; calculating the time offset value between the two ends, and completing time synchronization.

Abstract: A method and system for processing correction field information are provided. The method includes: receiving a packet, and obtaining a first correction value carried by the packet; obtaining first time information and second time information; obtaining a second correction value according to the first correction value and the first time information; setting the second correction value in the packet; setting the second time information in the packet; obtaining third time information and fourth time information; obtaining a third correction value according to the second correction value, the second time information, the third time information, and the fourth time information; and setting the third correction value in the packet. The processing of the time information and the processing of the correction field information are performed with a set of processing mechanism, and the implementation is simpler.

Abstract: A method, a device and a system for clock synchronization are provided. The method includes: under a first transfer mode, generating a first receiving timestamp by using a first link, and acquiring a first transmitting timestamp of a master clock device; under a second transfer mode, generating a second transmitting timestamp by using the first link, and acquiring a second receiving timestamp of the master clock device; and acquiring a time difference to the master clock device according to the first receiving timestamp, the first transmitting timestamp, the second transmitting timestamp and the second receiving timestamp, and realizing a clock synchronization with the master clock device by using the time difference. A slave clock device and a master clock device are provided in the embodiments of the present invention, as well as a system for clock synchronization.

Abstract: A time synchronization method includes: after sending a synchronization message to the opposite end, sending a following message where an ending time for sending the synchronization message is recorded; receiving a delay request message sent by the opposite end, and sending a delay response message where the initial time for receiving the delay request message is recorded; receiving the synchronization message and the following message, and recording the initial time for receiving the synchronization message and the ending time recorded in the following message for sending the synchronization message; sending a delay request message, and recording an ending time for sending the delay request message; receiving a delay response message, and recording an initial time recorded in the delay response message for the opposite end to receive the delay request message; calculating the time offset value between the two ends, and completing time synchronization.

Abstract: A method and system for processing correction field information are provided. The method includes: receiving a packet, and obtaining a first correction value carried by the packet; obtaining first time information and second time information; obtaining a second correction value according to the first correction value and the first time information; setting the second correction value in the packet; setting the second time information in the packet; obtaining third time information and fourth time information; obtaining a third correction value according to the second correction value, the second time information, the third time information, and the fourth time information; and setting the third correction value in the packet. The processing of the time information and the processing of the correction field information are performed with a set of processing mechanism, and the implementation is simpler.

Abstract: A method and device for improving clock stability are provided. The method includes: determining whether a difference between a current sender timestamp (ST) and a current receiver timestamp (RT) is a mutated value; pre-processing the ST and RT, if the difference between the ST and RT is a mutated value; acquiring a service clock according to the pre-processed ST and RT; and sending time division multiplex (TDM) data according to the service clock. Through the embodiments of the present disclosure, a packet delay variance (PDV) may be smoothed, the impairment of the PDV on clock recovery may be reduced, the quality of the clock recovery may be improved, and the problem of clock synchronization may be solved through the mutation processing on the timestamps.

Abstract: A precise-clock synchronization method and system and a precise-clock frequency/time synchronization device are provided. In the embodiments of the present invention, two time stamp engines are provided at a slave clock side. A relative time stamp engine provides a relative arrival time stamp. An absolute time stamp engine provides an absolute arrival time stamp. The frequency/time synchronization is calculated by using different time stamps obtained from different time stamp engines, so the frequency synchronization and time synchronization of the master clock and the slave clock may be separately accomplished, and one synchronization function may be enabled or disabled. Therefore, the frequency synchronization and time synchronization of the master clock and the slave clock do not interfere with each other, thus greatly reducing the occupied link bandwidth resources.

Abstract: A method and device for improving clock stability are provided. The method includes: determining whether a difference between a current sender timestamp (ST) and a current receiver timestamp (RT) is a mutated value; pre-processing the ST and RT, if the difference between the ST and RT is a mutated value; acquiring a service clock according to the pre-processed ST and RT; and sending time division multiplex (TDM) data according to the service clock.. Through the embodiments of the present disclosure, a packet delay variance (PDV) may be smoothed, the impairment of the PDV on clock recovery may be reduced, the quality of the clock recovery may be improved, and the problem of clock synchronization may be solved through the mutation processing on the timestamps.

Abstract: A precise-clock synchronization method and system and a precise-clock frequency/time synchronization device are provided. In the embodiments of the present invention, two time stamp engines are provided at a slave clock side. A relative time stamp engine provides a relative arrival time stamp. An absolute time stamp engine provides an absolute arrival time stamp. The frequency/time synchronization is calculated by using different time stamps obtained from different time stamp engines, so the frequency synchronization and time synchronization of the master clock and the slave clock may be separately accomplished, and one synchronization function may be enabled or disabled. Therefore, the frequency synchronization and time synchronization of the master clock and the slave clock do not interfere with each other, thus greatly reducing the occupied link bandwidth resources.

Abstract: A precise-clock synchronization method and system and a precise-clock frequency/time synchronization device are provided. In the embodiments of the present invention, two time stamp engines are provided at a slave clock side. A relative time stamp engine provides a relative arrival time stamp. An absolute time stamp engine provides an absolute arrival time stamp. The frequency/time synchronization is calculated by using different time stamps obtained from different time stamp engines, so the frequency synchronization and time synchronization of master clock and the slave clock may be separately accomplished, and one synchronization function may be enabled or disabled. Therefore, the frequency synchronization and time synchronization of the master clock and the slave clock do not interfere with each other, thus greatly reducing the occupied link bandwidth resources.

Abstract: A method and device for improving clock stability are provided. The method includes: determining whether a difference between a current sender timestamp (ST) and a current receiver timestamp (RT) is a mutated value; pre-processing the ST and RT, if the difference between the ST and RT is a mutated value; acquiring a service clock according to the pre-processed ST and RT; and sending time division multiplex (TDM) data according to the service clock.. Through the embodiments of the present disclosure, a packet delay variance (PDV) may be smoothed, the impairment of the PDV on clock recovery may be reduced, the quality of the clock recovery may be improved, and the problem of clock synchronization may be solved through the mutation processing on the timestamps.