Abstract: The present disclosure provides a memory and a method for forming the same. The memory includes: a substrate including a first region, a second region and a third region; a floating gate structure disposed on the second region of the substrate; a first side wall disposed on the floating gate structure; a first gate structure disposed on a side of the floating gate structure, wherein the first gate structure is electrically coupled with the floating gate structure; a dielectric structure disposed on a surface of the first gate structure; a source line structure disposed on a surface of the dielectric structure, wherein the source line structure is also disposed on a surface of the first region; and a word line gate structure disposed on the third region. Therefore, the performance of the memory can be improved.

Abstract: The present disclosure provides a memory structure and a method for forming the same. The memory structure includes: a substrate; a plurality of discrete composite structures disposed on the substrate, wherein a first opening is formed between adjacent composite structures, and each composite structure includes a first conductive structure, a floating gate structure disposed on both sides of the first conductive structure, an erasing gate structure disposed on the floating gate structure, a first isolation structure, a second isolation structure and a third isolation structure disposed on the erasing gate structure; a plurality of mutually independent source doped regions disposed in the substrate, wherein the plurality of source doped regions are in contact with bottom surfaces of the first conductive structure and the floating gate structure; and a word line structure disposed in the first opening. Therefore, the performance and integration of the memory structure can be improved.

Abstract: A substrate in a split-gate memory device has a memory cell region including a connecting subregion and a functional subregion. A source region is formed in the substrate, and first and second gate structures mirrored to each other are formed on the substrate on opposing sides of the source region. In the connecting subregion, control gates of the first and second gate structures and the source region are electrically connected by electrical connections. In the split-gate memory device, the arrangement of the functional and connecting subregions in the memory cell region and external connection of the control gates in the first and second gate structures and the source region in the connecting subregion, which are exposed by etching, by the electrical connections in the connecting subregion result in area savings of the memory cell region.

Abstract: A substrate in a split-gate memory device has a memory cell region including a connecting subregion and a functional subregion. A source region is formed in the substrate, and first and second gate structures mirrored to each other are formed on the substrate on opposing sides of the source region. In the connecting subregion, control gates of the first and second gate structures and the source region are electrically connected by electrical connections. In the split-gate memory device, the arrangement of the functional and connecting subregions in the memory cell region and external connection of the control gates in the first and second gate structures and the source region in the connecting subregion, which are exposed by etching, by the electrical connections in the connecting subregion result in area savings of the memory cell region.

Abstract: The present disclosure provides a memory and a method for forming the memory. The memory includes: a substrate including an erase region and a floating gate region, wherein the floating gate region is adjacent to the erase region, and both sides of the erase region are disposed with the floating gate region; a floating gate structure disposed on the floating gate region; a control gate structure disposed on the floating gate structure; and a word line gate structure disposed on the substrate on both sides of the erase region and the floating gate region, wherein the word line gate structure is in contact with a part of the control gate structure, and a first sidewall is disposed between the floating gate structure and the word line gate structure. The memory has good performance.

Abstract: A flash memory structure, a memory array and a fabrication method thereof are disclosed. In the flash memory structure, an erase gate structure is formed between two floating gates, and a word line structure is formed on an outer side of each of the two floating gates, with an oxide layer formed between the word line structure and the substrate. The flash memory structure can be fabricated with a simple process. The memory array employing the flash memory structure is capable of erase operations by means of a voltage applied on erase gate lines and of read operations by means of a voltage applied on word lines. This enables read operations at a lower voltage with less power consumed by the memory array. In addition, the memory array is more efficient and more durable.

Abstract: A flash memory structure, a memory array and a fabrication method thereof are disclosed. In the flash memory structure, an erase gate structure is formed between two floating gates, and a word line structure is formed on an outer side of each of the two floating gates, with an oxide layer formed between the word line structure and the substrate. The flash memory structure can be fabricated with a simple process. The memory array employing the flash memory structure is capable of erase operations by means of a voltage applied on erase gate lines and of read operations by means of a voltage applied on word lines. This enables read operations at a lower voltage with less power consumed by the memory array. In addition, the memory array is more efficient and more durable.

Abstract: Split-gate flash memory and forming method thereof are provided. The method includes: forming a first dielectric layer on a semiconductor substrate; forming a floating gate layer on the first dielectric layer; forming a mask layer on the floating gate layer; etching the mask layer until first groove exposing the floating gate layer is formed; forming a protective sidewall on sidewall of the first groove; forming a gate dielectric layer on bottom and the sidewall of the first groove; forming two control gates on the gate dielectric layer, the remained first groove serving as second groove; etching the gate dielectric layer and the floating gate layer at bottom of the second groove until third groove exposing the first dielectric layer is formed; forming a source in the semiconductor substrate under the third groove; and forming a second dielectric layer in the third groove. Reliability and durability of the memory are improved.

Abstract: A flash memory unit, a memory array and operation methods thereof are provided. The flash memory unit includes a semiconductor substrate, a first and a second bit line structures, a word line structure, a first and a second float gates, and a first and a second control gates. The semiconductor substrate has doping wells formed therein, constituting a source and a drain. The first and second bit line structures are respectively connected with the source and the drain. The word line structure is disposed between the first and second bit line structures. The first float gate is disposed between the first bit line structure and the word line, and the second float gate is disposed between the second bit line structure and the word line. The first control gate is disposed on the first float gate, and the second control gate is disposed on the second float gate.

Abstract: Split-gate flash memory and forming method thereof are provided. The method includes: forming a first dielectric layer on a semiconductor substrate; forming a floating gate layer on the first dielectric layer; forming a mask layer on the floating gate layer; etching the mask layer until first groove exposing the floating gate layer is formed; forming a protective sidewall on sidewall of the first groove; forming a gate dielectric layer on bottom and the sidewall of the first groove; forming two control gates on the gate dielectric layer, the remained first groove serving as second groove; etching the gate dielectric layer and the floating gate layer at bottom of the second groove until third groove exposing the first dielectric layer is formed; forming a source in the semiconductor substrate under the third groove; and forming a second dielectric layer in the third groove. Reliability and durability of the memory are improved.

Abstract: A flash memory unit, a memory array and operation methods thereof are provided. The flash memory unit includes a semiconductor substrate, a first and a second bit line structures, a word line structure, a first and a second float gates, and a first and a second control gates. The semiconductor substrate has doping wells formed therein, constituting a source and a drain. The first and second bit line structures are respectively connected with the source and the drain. The word line structure is disposed between the first and second bit line structures. The first float gate is disposed between the first bit line structure and the word line, and the second float gate is disposed between the second bit line structure and the word line. The first control gate is disposed on the first float gate, and the second control gate is disposed on the second float gate.

Abstract: An Electrically Erasable Programmable Read-Only Memory (EEPROM) and an EEPROM storage array are provided. The EEPROM storage array includes: at least one storage area, wherein the storage area comprises M word lines in a row direction, 8 bit lines in a column direction, 8 source lines in the column direction, and a plurality of storage units arranged in M rows and 8 columns, where M is a positive integer; and wherein gate electrodes of storage units in a same row are connected with a same word line, drain electrodes of storage units in a same column are connected with a same bit line, and source electrodes of storage units in a same column are connected with a same source line. The EEPROM's volume is reduced by connecting source electrodes of storage units in a same column to a same source line, and arranging the source lines in a column direction.

Abstract: A memory includes an array of memory cells including a plurality of memory cells with a common source, wherein each of the plurality of memory cells with a common source includes two sub-memory cells, each of the sub-memory cells corresponds to a bit line, and the respective bits are electrically independent. Each of the sub-memory cells in the memory according to the disclosure corresponds to a bit line, and the respective bit lines are electrically independent, thereby effectively avoiding interference to other memory cells which will not be programmed during a program operation.

Abstract: A semiconductor device fabrication method particularly suitable for the fabrication of a 90 nm embedded flash memory is disclosed. The method includes: forming a dielectric layer having a first thickness over a first device region and forming a dielectric layer having a second thickness different from the first thickness over a second device region, the dielectric layer having a first thickness serving as a tunnel oxide layer of a split-gate structure, the dielectric layer having a second thickness serving as a gate oxide layer of a MOS transistor. The method enables the fabrication of a MOS transistor including a gate oxide layer with a desired thickness.

Abstract: A semiconductor device fabrication method particularly suitable for the fabrication of a 90 nm embedded flash memory is disclosed. The method includes: forming a dielectric layer having a first thickness over a first device region and forming a dielectric layer having a second thickness different from the first thickness over a second device region, the dielectric layer having a first thickness serving as a tunnel oxide layer of a split-gate structure, the dielectric layer having a second thickness serving as a gate oxide layer of a MOS transistor. The method enables the fabrication of a MOS transistor including a gate oxide layer with a desired thickness.