Abstract: The disclosure provides an intelligent processing apparatus including a processor and a direct memory access (DMA) controller. The processor generates a read command to read data from a memory. An address generation circuit generates multiple first address signals to the memory. A data processing circuit receives data that the memory outputs in response to the multiple first address signals, and performs a data interception process on the data received from the memory according to the read command and a first configuration parameter. A data port transmits the data processed by the data processing circuit to the processor. The multiple first address signals include multiple non-consecutive address signals such that the data read from the memory and processed by the data processing circuit corresponds to n-dimensional data blocks, where n is a positive integer greater than 1.