Abstract: A hardware acceleration method and system based on a scale-invariant feature transform algorithm in the field of hardware acceleration design of algorithms is disclosed. The architecture mainly includes two parts: keypoint detection and descriptor generation. Four buffers between these two parts are ping-ponged to increase the system processing speed. In the keypoint detection part, firstly, multi-layer Gaussian pyramid and Gaussian difference pyramid are calculated in parallel; through parallel calculation, the keypoints and gradient magnitudes and orientations are obtained. In the descriptor generation part, a keypoint region division strategy based on the circular keypoint region is provided, and the parallel calculation of a main orientation calculation module and a descriptor generation module are implemented. Finally, the output is obtained through descriptor rearrangement and dimensionality reduction module.

Abstract: The disclosure discloses a reconfigurable hardware acceleration method and system for Gaussian pyramid construction and belongs to the field of hardware accelerator design. The system provided by the disclosure includes a static random access memory (SRAM) bank, a first in first out (FIFO) group, a switch network, a shift register array, an adder tree module, a demultiplexer, a reconfigurable PE array, and a Gaussian difference module. In the disclosure, according to the requirements of different scenarios and different tasks for the system, reconfigurable PE array resources can be configured to realize convolution calculations of different scales. The disclosure includes methods of fast and slow dual clock domain design, dynamic edge padding design, and input image partial sum reusing design.

Abstract: The disclosure discloses a reconfigurable hardware acceleration method and system for Gaussian pyramid construction and belongs to the field of hardware accelerator design. The system provided by the disclosure includes a static random access memory (SRAM) bank, a first in first out (FIFO) group, a switch network, a shift register array, an adder tree module, a demultiplexer, a reconfigurable PE array, and a Gaussian difference module. In the disclosure, according to the requirements of different scenarios and different tasks for the system, reconfigurable PE array resources can be configured to realize convolution calculations of different scales. The disclosure includes methods of fast and slow dual clock domain design, dynamic edge padding design, and input image partial sum reusing design.

Abstract: A storage device and a photoresist coating and developing machine having a storage device are disclosed. The storage device includes a frame and a plurality of layers of support plates disposed in sequence in the frame in a height direction of the frame, being used for receiving substrates to be exposed. The frame is provided with a plurality of layers of support members respectively associated with the plurality of layers of support plates, and each layer of the support plates is slidably mounted on the support member.

Abstract: A storage device and a photoresist coating and developing machine having a storage device are disclosed. The storage device includes a frame and a plurality of layers of support plates disposed in sequence in the frame in a height direction of the frame, being used for receiving substrates to be exposed. The frame is provided with a plurality of layers of support members respectively associated with the plurality of layers of support plates, and each layer of the support plates is slidably mounted on the support member.