Patents by Inventor Bingsen QIU

Bingsen QIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9369142
    Abstract: The present invention provides a multi-channel time-interleaved analog-to-digital converter, including: a clock generation circuit, configured to generate a work clock of the analog-to-digital converter; a channel ADC group, including M ADC channels, and configured to convert, under the control of the clock generation circuit and in a time division multiplexing manner, one high-speed analog input signal into M low-speed digital output signals; a channel mismatch detection circuit, configured to detect in real time timing skew errors of output signals of the M ADC channels; a signal compensation and reconstruction circuit, configured to perform, according to the timing skew parameters detected, compensation and reconstruction on the digital output signals output by the channel ADC group; and a signal combining circuit, configured to combine the M low-speed output signals that are of the channels and generated after the compensation by the signal compensation and reconstruction circuit.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: June 14, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Bingsen Qiu
  • Publication number: 20150381193
    Abstract: The present invention provides a multi-channel time-interleaved analog-to-digital converter, including: a clock generation circuit, configured to generate a work clock of the analog-to-digital converter; a channel ADC group, including M ADC channels, and configured to convert, under the control of the clock generation circuit and in a time division multiplexing manner, one high-speed analog input signal into M low-speed digital output signals; a channel mismatch detection circuit, configured to detect in real time timing skew errors of output signals of the M ADC channels; a signal compensation and reconstruction circuit, configured to perform, according to the timing skew parameters detected, compensation and reconstruction on the digital output signals output by the channel ADC group; and a signal combining circuit, configured to combine the M low-speed output signals that are of the channels and generated after the compensation by the signal compensation and reconstruction circuit.
    Type: Application
    Filed: June 23, 2015
    Publication date: December 31, 2015
    Inventor: Bingsen QIU