Patents by Inventor Bingsen Xie

Bingsen Xie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942465
    Abstract: Disclosed is a manufacturing method for an embedded structure. The method includes: preparing a temporary carrier board; preparing a second circuit layer on at least one of the upper surface and the lower surface of the temporary carrier board, and preparing a first dielectric layer to cover the second circuit layer; patterning and curing the first dielectric layer to form a cavity, mounting a device in the cavity, and performing hot-curing, wherein a surface of the device provided with a terminal faces an opening of the cavity; and preparing a second dielectric layer, wherein the device is embedded in the second dielectric layer, and a surface of the second dielectric layer is higher than a surface of the terminal by a preset value.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: March 26, 2024
    Assignee: Zhuhai ACCESS Semiconductor Co., Ltd.
    Inventors: Xianming Chen, Bingsen Xie, Benxia Huang, Lei Feng, Wenshi Wang
  • Publication number: 20220310529
    Abstract: Disclosed are a heat dissipation-electromagnetic shielding embedded packaging structure, a manufacturing method thereof, and a substrate. The heat dissipation-electromagnetic shielding embedded packaging structure includes: a dielectric layer including an upper surface and a lower surface, wherein at least one hollow cavity unit is disposed inside the dielectric layer; an insulating layer disposed in the hollow cavity unit, wherein the hollow cavity unit is partially filled with the insulating layer; an electronic element, wherein one end is embedded in the insulating layer, the other end is exposed in the hollow cavity unit, and the electronic element includes terminals; a through hole penetrating through the upper surface and the lower surface of the dielectric layer and communicating with the terminals; and a metal layer covering the six surfaces of the dielectric layer and the interior of the through hole to form a shielding layer and circuit layer respectively.
    Type: Application
    Filed: July 24, 2020
    Publication date: September 29, 2022
    Inventors: Xianming Chen, Bingsen Xie, Benxia Huang, Lei Feng
  • Publication number: 20220295646
    Abstract: A temporary carrier according to an embodiment of the present invention may include a core layer, a first Cu foil layer and a second Cu foil layer on surfaces of both sides of the core layer. Each of the first Cu foil layer and the second Cu foil layer may include double Cu foils which are physically attached together.
    Type: Application
    Filed: May 31, 2022
    Publication date: September 15, 2022
    Inventors: Xianming CHEN, Jian PENG, Jida ZHANG, Benxia HUANG, Lei FENG, Bingsen XIE, Jun GAO
  • Patent number: 11399440
    Abstract: A temporary carrier according to an embodiment of the present invention may include a core layer, a first Cu foil layer and a second Cu foil layer on surfaces of both sides of the core layer. Each of the first Cu foil layer and the second Cu foil layer may include double Cu foils which are physically attached together.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: July 26, 2022
    Assignee: ZHUHAI ACCESS SEMICONDUCTOR CO., LTD
    Inventors: Xianming Chen, Jian Peng, Jida Zhang, Benxia Huang, Lei Feng, Bingsen Xie, Jun Gao
  • Patent number: 11342273
    Abstract: Disclosed are a package structure of an integrated passive device and a manufacturing method thereof and a substrate. The method includes: providing an organic frame having a chip embedding cavity and a metal pillar, laminating at least one layer of first dielectric on an upper surface of the organic frame, and processing the first dielectric by photolithography to form an opening correspondingly above the chip embedding cavity; mounting an electronic component in the chip embedding cavity through the opening, the electronic component including an upper and lower electrodes; laminating and curing a second dielectric into the chip embedding cavity and on an upper surface of the first dielectric, thinning the first and second dielectrics to expose the upper and lower electrodes, upper and lower surfaces of the metal pillar; performing metal electroplating to form a circuit layer communicated with the upper and lower electrodes and the metal pillar.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: May 24, 2022
    Assignee: ZHUHAI ACCESS SEMICONDUCTOR CO., LTD
    Inventors: Xianming Chen, Yejie Hong, Benxia Huang, Lei Feng, Bingsen Xie
  • Publication number: 20220059520
    Abstract: Disclosed is a manufacturing method for an embedded structure. The method includes: preparing a temporary carrier board; preparing a second circuit layer on at least one of the upper surface and the lower surface of the temporary carrier board, and preparing a first dielectric layer to cover the second circuit layer; patterning and curing the first dielectric layer to form a cavity, mounting a device in the cavity, and performing hot-curing, wherein a surface of the device provided with a terminal faces an opening of the cavity; and preparing a second dielectric layer, wherein the device is embedded in the second dielectric layer, and a surface of the second dielectric layer is higher than a surface of the terminal by a preset value.
    Type: Application
    Filed: July 29, 2021
    Publication date: February 24, 2022
    Inventors: Xianming Chen, Bingsen Xie, Benxia Huang, Lei Feng, Wenshi Wang
  • Patent number: 11257713
    Abstract: A method for manufacturing an interposer board without a feature layer structure according to an embodiment of the present invention may include preparing a temporary carrier; forming an edge seal for the temporary carrier; laminating an insulating material onto upper and lower surfaces of the temporary carrier to form an insulating layer; forming a via on the insulating layer, filling the via with a metal; and removing the edge seal and removing the temporary carrier. An interposer board without a feature layer structure according to an embodiment of the present invention may include an insulating layer and a via-post layer embedded in the insulating layer, wherein the via-post has an end used as a pad.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: February 22, 2022
    Assignee: Zhuhai ACCESS Semiconductor Co., Ltd
    Inventors: Xianming Chen, Min Gu, Benxia Huang, Lei Feng, Bingsen Xie
  • Publication number: 20220045043
    Abstract: An embedded packaging structure according to an embodiment of the present disclosure includes an optical communication device embedded in a substrate, and a blocking wall surrounding the working face opening. The optical communication device may include a working face for emitting light or receiving light. The working face may be revealed by a working face opening from a first surface of the substrate. The blocking wall may extend beyond the first surface in a direction away from the first surface.
    Type: Application
    Filed: August 4, 2021
    Publication date: February 10, 2022
    Inventors: Xianming CHEN, Benxia HUANG, Lei FENG, Lina JIANG, Bingsen XIE, Jindong FENG
  • Publication number: 20210407922
    Abstract: Disclosed are a package structure of an integrated passive device and a manufacturing method thereof and a substrate. The method includes: providing an organic frame having a chip embedding cavity and a metal pillar, laminating at least one layer of first dielectric on an upper surface of the organic frame, and processing the first dielectric by photolithography to form an opening correspondingly above the chip embedding cavity; mounting an electronic component in the chip embedding cavity through the opening, the electronic component including an upper and lower electrodes; laminating and curing a second dielectric into the chip embedding cavity and on an upper surface of the first dielectric, thinning the first and second dielectrics to expose the upper and lower electrodes, upper and lower surfaces of the metal pillar; performing metal electroplating to form a circuit layer communicated with the upper and lower electrodes and the metal pillar.
    Type: Application
    Filed: September 23, 2020
    Publication date: December 30, 2021
    Inventors: Xianming CHEN, Yejie HONG, Benxia HUANG, Lei FENG, Bingsen XIE
  • Publication number: 20210410297
    Abstract: A temporary carrier according to an embodiment of the present invention may include a core layer, a first Cu foil layer and a second Cu foil layer on surfaces of both sides of the core layer. Each of the first Cu foil layer and the second Cu foil layer may include double Cu foils which are physically attached together.
    Type: Application
    Filed: September 30, 2020
    Publication date: December 30, 2021
    Inventors: Xianming CHEN, Jian PENG, Jida ZHANG, Benxia HUANG, Lei FENG, Bingsen XIE, Jun GAO
  • Publication number: 20210391213
    Abstract: A method for manufacturing an interposer board without a feature layer structure according to an embodiment of the present invention may include preparing a temporary carrier; forming an edge seal for the temporary carrier; laminating an insulating material onto upper and lower surfaces of the temporary carrier to form an insulating layer; forming a via on the insulating layer, filling the via with a metal; and removing the edge seal and removing the temporary carrier. An interposer board without a feature layer structure according to an embodiment of the present invention may include an insulating layer and a via-post layer embedded in the insulating layer, wherein the via-post has an end used as a pad.
    Type: Application
    Filed: October 19, 2020
    Publication date: December 16, 2021
    Inventors: Xianming CHEN, Min GU, Benxia HUANG, Lei FENG, Bingsen XIE
  • Patent number: 9852734
    Abstract: System and methods are provided for modifying audio signals. A waveform representing an audio signal changing over time is received. A first time length is selected. A first starting point in the waveform is selected. A first pair of adjacent segments of the waveform are determined based at least in part on the first starting point and the first time length. The first pair of adjacent segments each correspond to the first time length. A first difference measure associated with the first pair of adjacent segments is calculated. In response to the first difference measure being smaller than a threshold, compression or expansion of the waveform is performed based at least in part on the first time length and the first starting point.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: December 26, 2017
    Assignees: SYNAPTICS INCORPORATED, SYNAPTICS LLC
    Inventors: Zhuojin Sun, Bingsen Xie