Abstract: Electronic devices and methods are disclosed, including transistors with thick gate dielectric layers. Selected devices and methods shown include multiple layer gate dielectrics. Selected devices and methods shown include a gate dielectric with a first layer having a first width, and a second layer over the first layer, wherein the second layer has a second width smaller than the first width.

Abstract: A variety of applications can include devices implementing one or more fin field-effect transistors (FinFETs) with gate oxide thickness that address thicker gate oxide quality with minimum material loss in the fins of the FinFETs for high voltage devices. The gate oxides can be fabricated with thicker oxides than gate oxides of FinFETs used with capacitors in memory cells of memory arrays. These gate oxides can be formed as oxide liners by oxidation with use of a protective liner to maintain uniform composition of material for the fin during FinFET processing.

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include semiconductor devices having two or more fins, the fins separated by one or more inter-fin trenches. An isolation structure is included adjacent to the two or more fins, the isolation structure having a depth greater than the inter-fin trench depth.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to stacked gate transistors and methods of manufacture. The structure includes a stacked gate structure having a plurality of transistors with at least one floating node and at least one node to either ground or a supply voltage, and a contact to either of the ground or supply voltage and the at least one floating node being devoid of any contact.

Abstract: One illustrative method disclosed herein includes forming a conformal SMCM layer above a conformal high-k gate insulation layer within each of first and second replacement gate cavities (RGC), removing the SMCM layer from the first RGC while leaving the SMCM layer in position within the second RGC, forming a first conformal metal-containing material (MCM) layer above the gate insulation layer within the first RGC and above the SMCM layer in position within the second RGC, removing the first conformal MCM layer and the conformal SMCM layer positioned within the second RGC while leaving the first conformal MCM layer within the first RGC, and forming a second conformal MCM layer above the first conformal MCM layer positioned within the first RGC and above the gate insulation layer positioned within the second RGC.

Abstract: Structures for field-effect transistors and methods of forming a structure for field-effect transistors. A semiconductor layer includes first and second channel regions, a first field-effect transistor has a first gate dielectric layer over the first channel region, and a second field-effect transistor has a second gate dielectric layer over the second channel region. The first and second channel regions are each composed of an undoped section of an intrinsic semiconductor material, the first gate dielectric layer contains a first atomic concentration of a work function metal, and the second gate dielectric layer contains a second atomic concentration of the work function metal that is greater than the first atomic concentration of the work function metal in the first gate dielectric layer.

Abstract: One illustrative method disclosed herein includes forming at least one fin, forming a first recessed layer of insulating material adjacent the at least one fin and forming epi semiconductor material on the at least one fin. In this example, the method also includes forming a second recessed layer of insulating material above the first recessed layer of insulating material, wherein at least a portion of the epi semiconductor material is positioned above a level of the upper surface of the second recessed layer of insulating material, and forming a source/drain contact structure above the second recessed layer of insulating material, wherein the source/drain contact structure is conductively coupled to the epi semiconductor material.

Abstract: Structures for field-effect transistors and methods of forming a structure for field-effect transistors. A semiconductor layer includes first and second channel regions, a first field-effect transistor has a first gate dielectric layer over the first channel region, and a second field-effect transistor has a second gate dielectric layer over the second channel region. The first and second channel regions are each composed of an undoped section of an intrinsic semiconductor material, the first gate dielectric layer contains a first atomic concentration of a work function metal, and the second gate dielectric layer contains a second atomic concentration of the work function metal that is greater than the first atomic concentration of the work function metal in the first gate dielectric layer.

Abstract: A FinFET device is provided, which includes a semiconductor substrate, a fin structure and a dielectric material. The fin structure is extending from the semiconductor substrate, the fin structure having an upper fin section, a middle fin section and a lower fin section. The dielectric material is over the semiconductor substrate embedding a first portion of the lower fin section. The dielectric material forms shallow trench isolation regions of the FinFET device.

Abstract: One illustrative method disclosed herein includes forming at least one fin, forming a first recessed layer of insulating material adjacent the at least one fin and forming epi semiconductor material on the at least one fin. In this example, the method also includes forming a second recessed layer of insulating material above the first recessed layer of insulating material, wherein at least a portion of the epi semiconductor material is positioned above a level of the upper surface of the second recessed layer of insulating material, and forming a source/drain contact structure above the second recessed layer of insulating material, wherein the source/drain contact structure is conductively coupled to the epi semiconductor material.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to stacked gate transistors and methods of manufacture. The structure includes a stacked gate structure having a plurality of transistors with at least one floating node and at least one node to either ground or a supply voltage, and a contact to either of the ground or supply voltage and the at least one floating node being devoid of any contact.

Abstract: One illustrative method disclosed herein includes forming a conformal SMCM layer above a conformal high-k gate insulation layer within each of first and second replacement gate cavities (RGC), removing the SMCM layer from the first RGC while leaving the SMCM layer in position within the second RGC, forming a first conformal metal-containing material (MCM) layer above the gate insulation layer within the first RGC and above the SMCM layer in position within the second RGC, removing the first conformal MCM layer and the conformal SMCM layer positioned within the second RGC while leaving the first conformal MCM layer within the first RGC, and forming a second conformal MCM layer above the first conformal MCM layer positioned within the first RGC and above the gate insulation layer positioned within the second RGC.

Abstract: Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.

Abstract: Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.

Abstract: Devices and methods of growing unmerged epitaxy for fin field-effect transistor (FinFet) devices are provided. One method includes, for instance: obtaining a wafer having at least one source, at least one drain, and at least one fin; etching to expose at least a portion of the at least one fin; forming at least one sacrificial gate structure; and forming a first layer of an epitaxial growth on the at least one fin. One device includes, for instance: a wafer having at least one source, at least one drain, and at least one fin; a first layer of an epitaxial growth on the at least one fin; at least one second layer of an epitaxial growth superimposing the first layer of an epitaxial growth; and a first contact region over the at least one source and a second contact region over the at least one drain.

Abstract: Structures for a passive device of an integrated circuits and associated fabrication methods. A semiconductor substrate having raised fins and an dielectric isolation layer between the fins is formed. An etch stop layer is formed over the dielectric isolation layer between fins of a passive device. An interlayer dielectric layer is formed over the fins and etch stop layer. The interlayer dielectric layer is selectively etched to form an opening for conductive contact to the fins, where the etch stop layer prevents etching of the dielectric isolation layer. A conductive contact is formed to contact the plurality of fins, with the conductive contact terminating at the etch stop layer.

Abstract: A method and structure for a semiconductor device that includes one or more fin-type field effect transistors (FINFETs) and single-diffusion break (SDB) type isolation regions, which are within a semiconductor fin and define the active device region(s) for the FINFET(s). Asymmetric trenches are formed in a substrate through asymmetric cuts in sacrificial fins formed on the substrate. The asymmetric cuts have relatively larger gaps between fin portions that are closest to the substrate, and deeper portions of the asymmetric trenches are relatively wider than shallower portions. Channel regions are formed in the substrate below two adjacent fins. Source/drain regions of complementary transistors are formed in the substrate on opposite sides of the channel regions. The asymmetric trenches are filled with an insulator to form a single-diffusion break between two source/drain regions of different ones of the complementary transistors. Also disclosed is a semiconductor structure formed according to the method.

Abstract: Structures for a passive device of an integrated circuits and associated fabrication methods. A semiconductor substrate having raised fins and an dielectric isolation layer between the fins is formed. An etch stop layer is formed over the dielectric isolation layer between fins of a passive device. An interlayer dielectric layer is formed over the fins and etch stop layer. The interlayer dielectric layer is selectively etched to form an opening for conductive contact to the fins, where the etch stop layer prevents etching of the dielectric isolation layer. A conductive contact is formed to contact the plurality of fins, with the conductive contact terminating at the etch stop layer.

Abstract: A method and structure for a semiconductor device that includes one or more fin-type field effect transistors (FINFETs) and single-diffusion break (SDB) type isolation regions, which are within a semiconductor fin and define the active device region(s) for the FINFET(s). Asymmetric trenches are formed in a substrate through asymmetric cuts in sacrificial fins formed on the substrate. The asymmetric cuts have relatively larger gaps between fin portions that are closest to the substrate, and deeper portions of the asymmetric trenches are relatively wider than shallower portions. Channel regions are formed in the substrate below two adjacent fins. Source/drain regions of complementary transistors are formed in the substrate on opposite sides of the channel regions. The asymmetric trenches are filled with an insulator to form a single-diffusion break between two source/drain regions of different ones of the complementary transistors. Also disclosed is a semiconductor structure formed according to the method.

Abstract: The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure.