Abstract: An interdigital capacitor and a multiplying digital-to-analog conversion circuit, where the interdigital capacitor includes at least one first metal layer. The following components are disposed in each first metal layer: a first electrode; at least one first finger metal connected to the first electrode; a second electrode; and a plurality of second finger metals connected to the second electrode, and at least one third finger metal connected to the second electrode. The at least one first finger metal is alternately disposed with the plurality of second finger metals to form capacitors, and the at least one third finger metal is a dummy finger metal.

Abstract: A system facilitates authentication in situations where a pop-up window fails or is disallowed. If a browser application accessing a first webpage is not capable of presenting pop-up windows and redirects a user to a separate webpage for collecting information, the browser application, the absence of a JavaScript object indicating the pop-up window, or the inability to exchange data with a computing device associated with the first webpage is determined. In such a case, if valid information is received from the user, authorization data is provided to the computing device in the form of text included in a Uniform Resource Identifier (URI) for the first webpage. As a result, transactions may be authorized when a browser application is not capable of presenting pop-up windows.

Abstract: An interdigital capacitor and a multiplying digital-to-analog conversion circuit are provided. The interdigital capacitor includes at least one first metal layer. The following components are disposed in each first metal layer: a first electrode; at least one first finger metal connected to the first electrode; a second electrode; and a plurality of second finger metals connected to the second electrode, and at least one third finger metal connected to the second electrode. The at least one first finger metal is alternately disposed with the plurality of second finger metals to form capacitors, and the at least one third finger metal is a dummy (dummy) finger metal.

Abstract: A signal processing arrangement for a transmitter includes an in-phase modulator configured to receive an in-phase signal (I) and configured to modulate the in-phase signal (I); a quadrature modulator configured to receive a quadrature signal (Q) and configured to modulate the quadrature signal (Q); an in-phase demodulator configured to demodulate the modulated in-phase signal (I) and to output a demodulated in-phase signal (I); a quadrature demodulator configured to demodulate the modulated quadrature signal (Q) and to output a demodulated quadrature signal (Q); an in-phase harmonic filter configured to perform a filtering on harmonics in the demodulated in-phase signal (I) and to output an in-phase digital signal (I); and a quadrature harmonic filter configured to perform a filtering on harmonics in the demodulated quadrature signal (Q) and to output a quadrature digital signal (Q).

Abstract: Embodiments of the present invention provide a receiver and a wireless communications apparatus. The receiver includes: an attenuation circuit, configured to receive an input signal, and obtain a first signal according to the input signal; a low-noise amplification circuit, configured to receive the first signal, and obtain a second signal according to the first signal; an orthogonal down-frequency conversion circuit, configured to receive the second signal, and process the second signal to obtain an output signal; and a control circuit, configured to separately control the attenuation circuit and the low-noise amplification circuit according to power of an interference signal included in the output signal, so as to determine whether the attenuation circuit attenuates the input signal and whether the low-noise amplification circuit amplifies the first signal.

Abstract: A signal processing arrangement for a transmitter includes an in-phase modulator configured to receive an in-phase signal (I) and configured to modulate the in-phase signal (I); a quadrature modulator configured to receive a quadrature signal (Q) and configured to modulate the quadrature signal (Q); an in-phase demodulator configured to demodulate the modulated in-phase signal (I) and to output a demodulated in-phase signal (I); a quadrature demodulator configured to demodulate the modulated quadrature signal (Q) and to output a demodulated quadrature signal (Q); an in-phase harmonic filter configured to perform a filtering on harmonics in the demodulated in-phase signal (I) and to output an in-phase digital signal (I); and a quadrature harmonic filter configured to perform a filtering on harmonics in the demodulated quadrature signal (Q) and to output a quadrature digital signal (Q).

Abstract: Embodiments of the present invention provide a receiver and a wireless communications apparatus. The receiver includes: an attenuation circuit, configured to receive an input signal, and obtain a first signal according to the input signal; a low-noise amplification circuit, configured to receive the first signal, and obtain a second signal according to the first signal; an orthogonal down-frequency conversion circuit, configured to receive the second signal, and process the second signal to obtain an output signal; and a control circuit, configured to separately control the attenuation circuit and the low-noise amplification circuit according to power of an interference signal included in the output signal, so as to determine whether the attenuation circuit attenuates the input signal and whether the low-noise amplification circuit amplifies the first signal.

Abstract: A device for compensating temperature drift of a voltage controlled oscillator (VCO) is provided. The VCO has at least one varactor arranged for controlling an output frequency fOut of said VCO by applying a tuning voltage VTune and simultaneously applying a bias voltage VBias on a cathode and an anode of said at least one varactor, respectively. Said device comprises a monitoring circuit and a tuning circuit. Said monitoring circuit has an input arranged to receive said VTune and is arranged to monitor said VTune and further is arranged to activate said tuning circuit based on a value of said VTune, and said tuning circuit has an output connected to said anode and is arranged to output said VBias, wherein said tuning circuit further is arranged to tune said VCO by changing said VBias so as to compensate for a temperature drift of said VCO.

Abstract: A method and apparatus for generating a carrier frequency signal is disclosed. The method includes generating a first frequency signal; injecting a modulation signal at a first point of the two-point modulation architecture; generating a second frequency signal from the modulation signal; introducing the second frequency signal by mixing the first frequency signal and the second frequency signal to generate a mixed frequency signal and outputting the carrier frequency signal selected from the mixed frequency signal.

Abstract: A Digital Calibration System for a Phase Locked Loop includes a Tuning Voltage Controller configured to set the tuning voltage to a value; a Phase Difference Quantizer configured to output a phase difference after comparing a phase of the reference signal with a phase of the feedback signal; a Digital Controller configured to receive the phase difference of the PDQ and control a coarse tuning signal such that an average phase difference of the PDQ is 0; and a Frequency Calibration Logic configured to calibrate the feedback signal in response to the output of the DC.

Abstract: A method and a device for determining closed loop bandwidth characteristic of a Phase Locked Loop (PLL) (52) comprising a voltage controlled oscillator (VCO) (53) controlled by means of a tuning voltage (Vtune) is disclosed.

Abstract: A Digital Calibration System for a Phase Locked Loop includes a Tuning Voltage Controller configured to set the tuning voltage to a value; a Phase Difference Quantizer configured to output a phase difference after comparing a phase of the reference signal with a phase of the feedback signal; a Digital Controller configured to receive the phase difference of the PDQ and control a coarse tuning signal such that an average phase difference of the PDQ is 0; and a Frequency Calibration Logic configured to calibrate the feedback signal in response to the output of the DC.

Abstract: A method and a device for determining closed loop bandwidth characteristic of a Phase Locked Loop (PLL) (52) comprising a voltage controlled oscillator (VCO) (53) controlled by means of a tuning voltage (Vtune) is disclosed.

Abstract: A method and apparatus for generating a carrier frequency signal is disclosed. The method includes generating a first frequency signal; injecting a modulation signal at a first point of the two-point modulation architecture; generating a second frequency signal from the modulation signal; introducing the second frequency signal by mixing the first frequency signal and the second frequency signal to generate a mixed frequency signal and outputting the carrier frequency signal selected from the mixed frequency signal.