Abstract: Disclosed are systems and methods for providing transport layer encryption with an intermediate electronic message managing service interposed in a message path of an electronic message to be sent from a sending server to an intended receiving server across a computer network. To implement TLS in such a managed e-mail services context, given that a managed e-mail service is inserted into the message delivery path, the transport layer security protocols are simultaneously established along both the link from the sending server to the managed e-mail service and from the receiving server to the managed e-mail service, with the managed e-mail service providing a “proxy” connection for communication between the sending server and the receiving server.

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

Abstract: An erase methodology of flash memory cells in a multi-bit memory array with bits disposed in normal and complimentary locations. An erase verify of bits in the normal locations is performed and if a bit in the normal location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the normal bit and the complimentary bit. An erase verify of bits in the complimentary locations is performed and if a bit in the complimentary location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the complimentary and the normal bit locations. If the bits pass the erase verify, the bits are subjected to a soft programming verify. If the bits are overerased and if the soft programming pulse count has not been reached a soft programming pulse is applied to the overerased bit.

Abstract: A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.

Abstract: A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.

Abstract: The present invention relates to novel 4-(1H-benzimidazol-2-yl)[1,4]diazepane derivatives of formula (1): and stereoisomers thereof, and pharmaceutically acceptable salts thereof which are useful as histamine receptor antagonists and tachykinin receptor antagonist. Such antagonists are useful in the treatment of allergic rhinitis, including seasonal rhinitis and sinusitis; inflammatory bowel diseases, including Crohn's disease and ulcerative colitis; asthma; bronchitis; and emesis.

Abstract: The present invention relates to novel 4-(1H-benzimidazol-2-yl)[1,4]diazepane derivatives of formula 1

Abstract: The present invention relates to substituted piperazinone derivatives of formula (1) or stereoisomers, or pharmaceutically acceptable salts thereof and their use as tachykinin receptor antagonists. Such antagonists are useful in the treatment of tachykinin-mediated diseases and conditions disclosed herein including: asthma, cough, and bronchitis. The present invention also relates to intermediates useful in the preparation of compounds of formula (1).

Abstract: The present invention relates to substituted pyrrolidinyl-3-yl-alkyl-piperidines, their stereoisomers, and pharmaceutically acceptable salts thereof and processes for preparation of the same. The compounds of the present invention are useful in their pharmacological activities such as tachykinin antagonism, especially substance P and neurokinin A antagonism, and the like. Compounds having the property of tachykinin antagonism are indicated for conditions associated with neurogenic inflammation and other diseases described herein.

Abstract: The present invention relates to substituted piperazinone derivatives (compounds of formula (1)) or stereoisomers, or pharmaceutically acceptable salts thereof and their use as tachykinin receptor antagonists. Such antagonists are useful in the treatment of tachykinin-mediated diseases and conditions disclosed herein including: asthma, cough, and bronchitis. The present invention also relates to intermediates useful in the preparation of compounds of formula (1).

Abstract: The present invention relates to substituted piperazine derivatives (herein referred to as compounds or compounds of formula (1)) or stereoisomers, or pharmaceutically acceptable salts thereof and their use as tachykinin receptor antagonists. Such antagonists are useful in the treatment of tachykinin-mediated diseases and conditions disclosed herein including: asthma, cough, and bronchitis.

Abstract: The present invention relates to substituted pyrrolidinyl-3-yl-alkyl-piperidines, their stereoisomers, and pharmaceutically acceptable salts thereof and processes for preparation of the same. The compounds of the present invention are useful in their pharmacological activities such as tachykinin antagonism, especially substance P and neurokinin A antagonism, and the like. Compounds having the property of tachykinin antagonism are indicated for conditions associated with neurogenic inflammation and other diseases described herein.

Abstract: The present invention relates to substituted pyrrolidinyl-3-yl-alkyl-piperidines, their stereoisomers, and pharmaceutically acceptable salts thereof and processes for preparation of the same. The compounds of the present invention are useful in their pharmacological activities such as tachykinin antagonism, especially substance P and neurokinin A antagonism, and the like. Compounds having the property of tachykinin antagonism are indicated for conditions associated with neurogenic inflammation and other diseases described herein.

Abstract: The present invention relates to novel substituted alkyldiamine derivatives and pharmaceutically acceptable salts thereof which are useful tachykinin antagonists. Such antagonists are useful in the treatment of tachykinin-mediated diseases and conditions including asthma, cough, and bronchitis.