Patents by Inventor Binh Vo
Binh Vo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12137673Abstract: Provided are a multi-function device for intensive shrimp farming and intensive shrimp farming systems using this device. The system comprises: shrimp ponds (100) with brackish water pumped from rivers or seas then treated with chemicals, sedimentation and micro-organisms; at least one multifunction device (200) to generate water flow, dissolve molecular oxygen, deliver and dispense shrimp feed and provide solution containing minerals, micro-organisms and other additives; pure oxygen supply device (300) capable of generating oxygen from the air to supply oxygen with purity higher than 90% to water in intensive culture pond to achieve consistently higher concentrations of dissolved oxygen saturated dissolved oxygen concentration; a network of porous sheets floats on the water to reduce the diffusion of oxygen molecules from the water to the air; and a network of lights for providing artificial light to change the feeding cycle of shrimp with industrial and natural food.Type: GrantFiled: April 15, 2022Date of Patent: November 12, 2024Assignee: RYNAN TECHNOLOGIES—VIETNAM JOINT STOCK COMPANYInventors: Thanh My Nguyen, Quoc Toan Tran, Vu Khanh Vo, Quoc Viet Vo, Le Nhut Hao Huynh, Minh Chau Bui, Quoc Cuong Hong, Huynh Ngoc Duy To, Thi Tu Trinh Nguyen, Thai Binh Pham, Bao Dang Pham
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Patent number: 8516322Abstract: A programmable integrated circuit may contain multiple logic blocks. Computing equipment may be used to run automated tools that process a design for the programmable integrated circuit to perform corresponding circuit tests. A translation tool may translate a transistor-level description of circuitry on the programmable integrated circuit into a gate-level description. A block-level test configuration data generation tool may generate block-level test configuration data files. The test configuration data files may be used as constraints for an automatic test pattern generation tool that produces block-level test vectors. A full-chip propagation tool may use the block-level test vectors, block-level test configuration data files, and full-chip constraints to produce corresponding full-chip test configuration data and full-chip test vectors for testing the integrated circuit. A translation tool may convert the configuration data and test vectors into a tester file.Type: GrantFiled: September 28, 2009Date of Patent: August 20, 2013Assignee: Altera CorporationInventors: Jayabrata Ghosh Dastidar, Alok Shreekant Doshi, Binh Vo, Kalyana Ravindra Kantipudi, Sergey Timokhin
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Patent number: 8010510Abstract: A tokenized stream including n tokens, each token including two or more portions, is received and a first sort order based on a sort of a set of the first portions of the n tokens is determined. The first sort order is applied to reorder a set of the second portions of the n tokens. The above steps are repeated to determine a sort order based on a set of portions of the n tokens and to apply the sort order to another set of portions of the n tokens column until a cth set of portions been reordered by a (c?1)th sort order. The variable c is a desired number of sets to be sorted. The variables c and n are whole numbers and the n tokens are dispersed during reordering.Type: GrantFiled: July 2, 2008Date of Patent: August 30, 2011Assignee: Google Inc.Inventors: Binh Vo, Gurmeet Singii Manku
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Patent number: 7685485Abstract: Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysis is performed on interconnect resources related to failing paths. The resources on the paths are then tallied to create a histogram of resources. These resources are then be fed into an Adaptive Failure Isolation (AFI) tool to auto-generate verification patterns. A tester uses the verification patterns to isolate failed interconnect resources.Type: GrantFiled: October 30, 2003Date of Patent: March 23, 2010Assignee: Altera CorporationInventors: Binh Vo, Wan-Pin Hung, David Huang, Peter Boyle, Qi Richard Chen, Kaiyu Ren, Adam J. Wright, John DiCosola, Laiq Chughtai, Seng Yew Lim
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Patent number: 7571412Abstract: A method for generating automatic design characterization patterns for integrated circuits (IC) is provided. The method includes selecting a routing scheme from a file containing the device description of the routings of the IC. The routing scheme may be of a phase locked loop, clock tree, delay element, or input output block in one embodiment. Resource types for the routing scheme are identified and a path is defined, within constraints, between the resources. Once a path is defined, alternate paths are defined by retracing the path within constraints from an end of the path to the beginning of the path. An alternative path is then built and the alternative path shares a portion of the path previously defined. A computing system providing the functionality of the method is also provided.Type: GrantFiled: March 15, 2006Date of Patent: August 4, 2009Assignee: Altera CorporationInventors: Hung Hing Anthony Pang, Binh Vo, Souvik Ghosh
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Publication number: 20080040375Abstract: The present invention provides efficient window partitioning algorithms for entropy-encoding. The present invention enhances compression performance of entropy encoding based on the approach of modeling a dataset with the frequencies of its n-grams. The present invention may then employ approximation algorithms to compute good partitions in time O(s*log s) and O(s) respectively, for any data segment S with length s.Type: ApplicationFiled: October 12, 2007Publication date: February 14, 2008Inventors: Binh Vo, Kiem-Phong Vo
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Patent number: 7024327Abstract: Programmable circuits have a programmable interconnect structure that connects programmable circuit elements. Tests patterns can be automatically generated for the programmable circuit elements and interconnections on a programmable circuit. A connectivity graph represents programmable interconnections and functions as nodes. Tests routes are generated that connect the nodes in the connectivity graph between control points and observation points on the programmable circuit. The routes are grouped into configuration patterns that can be tested in one test cycle. Test vectors are then applied to the routes to determine if the interconnects and circuit functions are operable. Systems and methods of the present invention automatically create test patterns for a programmable circuit to reduce engineer time. The present invention also reduces test time and resources by increasing the number of interconnections and circuit elements tested in each configuration pattern.Type: GrantFiled: December 18, 2002Date of Patent: April 4, 2006Assignee: Altera CorporationInventors: Jayabrata Ghosh Dastidar, Adam Wright, Hung Hing Anthony Pang, Binh Vo, Ajay Nagarandal, Paul J. Tracy, Michael Harms
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Publication number: 20060031673Abstract: A method and system for detecting that a software system has been infected by software that attempts to hide properties related to the software system is provided. A detection system identifies that a suspect operating system has been infected by malware by comparing properties related to the suspect operating system as reported by the suspect operating system to properties as reported by another operating system that is assumed to be clean. The detection system compares the reported properties to the actual properties to identify any significant differences. A significant difference, such as the presence of an actual file not reported by the suspect operating system, may indicate that the suspect storage device is infected.Type: ApplicationFiled: November 23, 2004Publication date: February 9, 2006Applicant: Microsoft CorporationInventors: Douglas Beck, Aaron Johnson, Roussi Roussev, Chad Verbowski, Binh Vo, Yi-Min Wang
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Publication number: 20050055367Abstract: The present invention provides efficient window partitioning algorithms for entropy-encoding. The present invention enhances compression performance of entropy encoding based on the approach of modeling a dataset with the frequencies of its n-grams. The present invention may then employ approximation algorithms to compute good partitions in time O(s*log s) and O(s) respectively, for any data segment S with length s.Type: ApplicationFiled: July 19, 2004Publication date: March 10, 2005Inventors: Binh Vo, Kiem-Phong Vo
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Publication number: 20050044294Abstract: The present invention provides efficient target file window matching within the source file for delta compressors.Type: ApplicationFiled: July 19, 2004Publication date: February 24, 2005Inventors: Binh Vo, Kiem-Phong Vo
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Publication number: 20050022085Abstract: Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysis is performed on interconnect resources related to failing paths. The resources on the paths are then tallied to create a histogram of resources. These resources are then be fed into an Adaptive Failure Isolation (AFI) tool to auto-generate verification patterns. A tester uses the verification patterns to isolate failed interconnect resources.Type: ApplicationFiled: October 30, 2003Publication date: January 27, 2005Applicant: Altera CorporationInventors: Binh Vo, Wan-Pin Hung, David Huang, Peter Boyle, Qi Chen, Kaiyu Ren, Adam Wright, John DiCosola, Laiq Chughtai, Seng Lim
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Patent number: 6171463Abstract: The present invention relates to the electrophoretic separation of bio-organic molecules using a slab gel electrophoresis apparatus having a pair of spaced, confronting plates defining a multi-lane separation zone adapted to hold a separation medium and an upper loading zone. In one aspect of the invention, at least one of the plates is shaped to provide an expanded loading zone. The plate-to-plate distance within the expanded loading zone is greater than the plate-to-plate width within the separation zone. In another aspect of the invention, a comb is provided with each tooth having a gradual taper beginning at a support member and extending along most of the tooth's longitudinal axis, and a sharp taper beginning immediately beyond the gradual taper and extending to the end of the tooth.Type: GrantFiled: April 28, 1999Date of Patent: January 9, 2001Assignee: The Perkin-Elmer CorporationInventors: Barton G. Selby, Johan Goudberg, Binh Vo, David Clark, Thomas Sch{grave over (e)}fer, Munechika Sakabe
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Patent number: 5993628Abstract: The present invention relates to the electrophoretic separation of bio-organic molecules using a slab gel electrophoresis apparatus having a pair of spaced, confronting plates defining a multi-lane separation zone adapted to hold a separation medium and an upper loading zone. In one aspect of the invention, at least one of the plates is shaped to provide an expanded loading zone. The plate-to-plate distance within the expanded loading zone is greater than the plate-to-plate width within the separation zone. In another aspect of the invention, a comb is provided with each tooth having a gradual taper beginning at a support member and extending along most of the tooth's longitudinal axis, and a sharp taper beginning immediately beyond the gradual taper and extending to the end of the tooth.Type: GrantFiled: April 17, 1998Date of Patent: November 30, 1999Assignee: The Perkin-Elmer CorporationInventors: Barton G. Selby, Johan Goudberg, Binh Vo, David Clark