Abstract: The invention discloses a three-dimensional 1S1C memory based on a ring capacitor and a preparation method. The memory includes: a horizontal peripheral electrode layer including a first dielectric layer and a first metal electrode layer alternately stacked and grown on a substrate and provided with trenches penetrating in a vertical direction and holes penetrating in the vertical direction, a vertical functional layer, and a capacitive dielectric layer. An annular groove is disposed outside each hole. The annular groove surrounds the holes and vertically cuts off the peripheral electrode layer. The annular groove is evenly filled with a capacitive dielectric layer. A top of the second metal electrode layer is extended to a surface of a topmost first dielectric layer to form a bit line electrode and is connected to a bit line. A region where the second metal electrode layer faces the first metal electrode layer forms a memory cell.

Abstract: Disclosed are an OTS-based dynamic storage structure and an operation method thereof. The OTS-based dynamic storage structure includes a plurality of storage units distributed in an array, and each storage unit includes an OTS gating transistor and a storage capacitor. The OTS gating transistor has two states, namely, high resistance state and low resistance state. When the voltage across the OTS gating transistor exceeds the threshold voltage Vth, the OTS gating transistor is switched from the high resistance state to the low resistance state. When the voltage across the OTS gating transistor in the low resistance state is lower than the holding voltage Vhold, the OTS gating transistor is switched from the low resistance state to the high resistance state.

Abstract: Disclosed are an OTS-based dynamic storage structure and an operation method thereof. The OTS-based dynamic storage structure includes a plurality of storage units distributed in an array, and each storage unit includes an OTS gating transistor and a storage capacitor. The OTS gating transistor has two states, namely, high resistance state and low resistance state. When the voltage across the OTS gating transistor exceeds the threshold voltage Vth, the OTS gating transistor is switched from the high resistance state to the low resistance state. When the voltage across the OTS gating transistor in the low resistance state is lower than the holding voltage Vhold, the OTS gating transistor is switched from the low resistance state to the high resistance state.

Abstract: A method for operating a dynamic memory is provided, and the method includes the following steps. A refresh operation is performed on the dynamic memory according to predetermined interval time T, an operation command is received in real time at the same time, a read operation is performed on a selected memory cell according to position information of the selected memory cell in the operation command when the operation command is received, and state data read in the read operation is temporarily stored in a read buffer. The interval time T is less than time t required for a voltage value of a capacitor in the memory cell to drop to a critical capacitor voltage value for the read operation to correctly read the state data of the memory cell during a write operation. According to operation command type information in the operation command, corresponding operations are performed on the selected memory cell.

Abstract: A method for operating a dynamic memory is provided, and the method includes the following steps. A refresh operation is performed on the dynamic memory according to predetermined interval time T, an operation command is received in real time at the same time, a read operation is performed on a selected memory cell according to position information of the selected memory cell in the operation command when the operation command is received, and state data read in the read operation is temporarily stored in a read buffer. The interval time T is less than time t required for a voltage value of a capacitor in the memory cell to drop to a critical capacitor voltage value for the read operation to correctly read the state data of the memory cell during a write operation. According to operation command type information in the operation command, corresponding operations are performed on the selected memory cell.

Abstract: Coupled-cavity vertical cavity surface emitting lasers (VCSELs) are provided by the present disclosure. The coupled-cavity VCSEL can comprise a VCSEL having a first mirror, a gain medium disposed above the first mirror, and a second mirror disposed above the gain medium, wherein a first cavity is formed by the first mirror and the second mirror. A second cavity is optically coupled to the VCSEL and configured to reflect light emitted from the VCSEL back into the first cavity of the VCSEL. In some embodiments, the second cavity can be an external cavity optically coupled to the VCSEL through a coupling component. In some embodiments, the second cavity can be integrated with the VCSEL to form a monolithic coupled-cavity VCSEL. A feedback circuit can control operation of the coupled-cavity VCSEL so the output comprises a target high frequency signal.

Abstract: A silicon interposer may include an on-chip DC blocking capacitor, comprising: a first electrical connection to couple to a supply voltage and to cathodes of a plurality of photodiodes formed in a two-dimensional photodiode array on a first substrate, and a second electrical connection to couple to ground and to ground inputs of a plurality of transimpedance amplifiers on a second substrate; wherein the on-chip DC blocking capacitor is configured to be shared among a plurality of receiver circuits comprising the plurality of photodiodes and the plurality of transimpedance amplifiers; and wherein the silicon interposer comprises a substrate separate from the first substrate and the second substrate.

Abstract: Coupled-cavity vertical cavity surface emitting lasers (VCSELs) are provided by the present disclosure. The coupled-cavity VCSEL can comprise a VCSEL having a first mirror, a gain medium disposed above the first mirror, and a second mirror disposed above the gain medium, wherein a first cavity is formed by the first mirror and the second mirror. A second cavity is optically coupled to the VCSEL and configured to reflect light emitted from the VCSEL back into the first cavity of the VCSEL. In some embodiments, the second cavity can be an external cavity optically coupled to the VCSEL through a coupling component. In some embodiments, the second cavity can be integrated with the VCSEL to form a monolithic coupled-cavity VCSEL. A feedback circuit can control operation of the coupled-cavity VCSEL so the output comprises a target high frequency signal.

Abstract: A silicon interposer may include an on-chip DC blocking capacitor, comprising: a first electrical connection to couple to a supply voltage and to cathodes of a plurality of photodiodes formed in a two-dimensional photodiode array on a first substrate, and a second electrical connection to couple to ground and to ground inputs of a plurality of transimpedance amplifiers on a second substrate; wherein the on-chip DC blocking capacitor is configured to be shared among a plurality of receiver circuits comprising the plurality of photodiodes and the plurality of transimpedance amplifiers; and wherein the silicon interposer comprises a substrate separate from the first substrate and the second substrate.

Abstract: A VCSEL device includes a substrate and a first DBR structure disposed on the substrate. The VCSEL device further includes a cathode contact disposed on a top surface of the first DBR structure. In addition, the VCSEL device includes a VCSEL mesa that is disposed on the top surface of the first DBR structure. The VCSEL mesa includes a quantum well, a non-circularly-shaped oxide aperture region disposed above the quantum well, and a second DBR structure disposed above the non-circularly-shaped oxide aperture region. In addition, the VCSEL mesa includes a selective polarization structure disposed above the second DBR structure and an anode contact disposed above the selective polarization structure.

Abstract: A VCSEL transmitter includes a first VCSEL terminal disposed on a substrate and a second VCSEL terminal adjacent thereto. The transmitter also includes a first diffraction element within a first optical path of the first VCSEL terminal which receives and changes a first direction of a first light transmission having a low-order Laguerre Gaussian mode emitted from the first VCSEL terminal. The transmitter further includes a second diffraction element within a second optical path of the second VCSEL terminal which receives the second light transmission and converts the received light into a high-order Laguerre Gaussian mode. The transmitter also includes a mode combiner to direct the first light transmission into a lens which directs the light into a multi-mode optical fiber.

Abstract: A VCSEL device includes a substrate and a first DBR structure disposed on the substrate. The VCSEL device further includes a cathode contact disposed on a top surface of the first DBR structure. In addition, the VCSEL device includes a VCSEL mesa that is disposed on the top surface of the first DBR structure. The VCSEL mesa includes a quantum well, a non-circularly-shaped oxide aperture region disposed above the quantum well, and a second DBR structure disposed above the non-circularly-shaped oxide aperture region. In addition, the VCSEL mesa includes a selective polarization structure disposed above the second DBR structure and an anode contact disposed above the selective polarization structure.

Abstract: A VCSEL transmitter includes aa first VCSEL terminal disposed on a substrate and a second VCSEL terminal adjacent thereto. The transmitter also includes a first diffraction element within a first optical path of the first VCSEL terminal which receives and changes a first direction of a first light transmission having a low-order Laguerre Gaussian mode emitted from the first VCSEL terminal. The transmitter further includes a second diffraction element within a second optical path of the second VCSEL terminal which receives the second light transmission and converts the received light into a high-order Laguerre Gaussian mode. The transmitter also includes a mode combiner to direct the first light transmission into a lens which directs the light into a multi-mode optical fiber.

Abstract: An example system may include a first vertical cavity surface emitting laser (VCSEL) that includes a first integrated polarization locking structure to produce a polarized optical data signal. The system may also comprise a second VCSEL that includes a second integrated polarization locking structure, the second integrated polarization locking structure orthogonal to the first integrated polarization locking structure, to produce an orthogonally polarized optical data signal. Lenses may be disposed on the substrate opposite the first VCSEL, to collimate the polarized optical data signal, and opposite the second VCSEL to collimate the orthogonally polarized optical data signal. A polarization division multiplexer may combine the first collimated polarized optical data signal and the second collimated orthogonally polarized optical data signal.

Abstract: An example system may include a first vertical cavity surface emitting laser (VCSEL) that includes a first integrated polarization locking structure to produce a polarized optical data signal. The system may also comprise a second VCSEL that includes a second integrated polarization locking structure, the second integrated polarization locking structure orthogonal to the first integrated polarization locking structure, to produce an orthogonally polarized optical data signal. Lenses may be disposed on the substrate opposite the first VCSEL, to collimate the polarized optical data signal, and opposite the second VCSEL to collimate the orthogonally polarized optical data signal. A polarization division multiplexer may combine the first collimated polarized optical data signal and the second collimated orthogonally polarized optical data signal.