Abstract: A cascaded delta-sigma modulator includes a first stage delta-sigma modulator (10A) having first adder (2) followed by first (3) and second (6) integrators, a second adder (4), and a quantizer (7) the output of which is fed back to the first adder by an A/D (9). A gain circuit (5) is also connected between the first integrator and the second adder. The quantizer output is coupled by interstage circuitry to a second stage converter (100B) having a transfer function represented by the expression OUT(z)=z?nIN(z)+G(z)E2(z). An error cancellation circuit (12) includes inputs coupled to the output of the quantizer and an output of the second stage converter so as to provide a flat transfer function of the cascaded first stage delta-sigma modulator and second stage converter and the error cancellation circuit, despite non-flatness in a transfer function of the first stage delta-sigma modulator.

Abstract: A cascaded delta-sigma modulator includes a first stage delta-sigma modulator (10A) having first adder (2) followed by first (3) and second (6) integrators, a second adder (4), and a quantizer (7) the output of which is fed back to the first adder by an A/D (9). A gain circuit (5) is also connected between the first integrator and the second adder. The quantizer output is coupled by interstage circuitry to a second stage converter (100B) having a transfer function represented by the expression OUT(z)=z?nIN(z)+G(z)E2(z). An error cancellation circuit (12) includes inputs coupled to the output of the quantizer and an output of the second stage converter so as to provide a flat transfer function of the cascaded first stage delta-sigma modulator and second stage converter and the error cancellation circuit, despite non-flatness in a transfer function of the first stage delta-sigma modulator.

Abstract: A bottom die and a top die stacked on the bottom die are configured to provide a daisy chain function. Both die include an input/output function control bonding pad (20G), a first bonding pad (20C) controllable to function as either an input or an output, and a second bonding pad (20E) controllable to function as either an output or an electrically floating pad in response to a corresponding input/output function control signal. The top die (30) is stacked on the bottom die (20) and the first bonding pad (20C) of the bottom die (20) is wire bonded to the first bonding pad (30C) of the top die (30). A first reference voltage (VDD) on the function control bonding pad of the bottom die configures its first bonding pad as an output and its second bonding pad as electrically floating, and a second reference voltage (VSS) on the function control bonding pad of the top die configures its first bonding pad as an input and its second bonding pad as an output, to thereby provide the daisy chain function.

Abstract: A bottom die and a top die stacked on the bottom die are configured to provide a daisy chain function. Both die include an input/output function control bonding pad (20G), a first bonding pad (20C) controllable to function as either an input or an output, and a second bonding pad (20E) controllable to function as either an output or an electrically floating pad in response to a corresponding input/output function control signal. The top die (30) is stacked on the bottom die (20) and the first bonding pad (20C) of the bottom die (20) is wire bonded to the first bonding pad (30C) of the top die (30). A first reference voltage (VDD) on the function control bonding pad of the bottom die configures its first bonding pad as an output and its second bonding pad as electrically floating, and a second reference voltage (VSS) on the function control bonding pad of the top die configures its first bonding pad as an input and its second bonding pad as an output, to thereby provide the daisy chain function.

Abstract: An integrator circuit includes an input conductor for conducting an input current, a first amplifier stage having a first input coupled to the input conductor and a second input coupled to receive a reference voltage and a second amplifier stage having a output and an input coupled to an output of the first amplifier stage. An integrating capacitor is coupled between the first input of the first amplifier stage and the output of the second amplifier stage, and a compensation capacitor comprised of an MOS capacitor is coupled between the input and the output of the second amplifier stage. The integrator circuit is especially adapted for use in a CT scanner data acquisition system.