Patents by Inventor Binny S. Gill
Binny S. Gill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20120151148Abstract: Systems and methods for background destaging storage tracks from cache when one or more hosts are idle are provided. One system includes a write cache configured to store a plurality of storage tracks and configured to be coupled to one or more hosts, and a processor coupled to the write cache. The processor includes code that, when executed by the processor, causes the processor to perform the method below. One method includes monitoring the write cache for write operations from the host(s) and determining if the host(s) is/are idle based on monitoring the write cache for write operations from the host(s). The storage tracks are destaged from the write cache if the host(s) is/are idle and are not destaged from the write cache if one or more of the hosts is/are not idle. Also provided are physical computer storage mediums including a computer program product for performing the above method.Type: ApplicationFiled: December 10, 2010Publication date: June 14, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent C. BEARDSLEY, Michael T. BENHASE, Binny S. GILL, Lokesh M. GUPTA, Sonny E. WILLIAMS
-
Publication number: 20120151147Abstract: Systems and methods for managing destage conflicts in cache are provided. One system includes a cache partitioned into multiple ranks configured to store multiple storage tracks and a processor coupled to the cache. The processor is configured to perform the following method. One method includes allocating an amount of storage space in the cache to each rank and monitoring a current amount of storage space used by each rank with respect to the amount of storage space allocated to each respective rank. The method further includes destaging storage tracks from each rank until the current amount of storage space used by each respective rank is equal to a predetermined minimum amount of storage space with respect to the amount of storage space allocated to each rank. Also provided are physical computer storage mediums including code that, when executed by a processor, cause the processor to perform the above method.Type: ApplicationFiled: December 10, 2010Publication date: June 14, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent C. BEARDSLEY, Michael T. BENHASE, Binny S. GILL, Lokesh M. GUPTA, Sonny E. WILLIAMS
-
Patent number: 8196119Abstract: A computer program product for code coverage utilizing efficient dynamic mutation of logic (EDML) are provided. A source code is read, and instrumentation points are located. Self Modifying Code (SMC) is inserted at the instrumentation points producing instrumented code. Additional functions are inserted in the source code to enable read and/or reset of code coverage statistics. The instrumented code is compiled, and executables are run for a period of time during which zero or more instrumentation points are executed. In response to executing instrumentation points, instructions are executed to record execution of the instrumented code. Instructions of the instrumented code overwrite themselves at certain points so that a next execution of the instrumentation points skips over the instrumented code at the certain points. Code coverage statistics are gathered and recorded. The code coverage statistics are reset to begin another period of time for gathering code coverage statistics.Type: GrantFiled: March 28, 2008Date of Patent: June 5, 2012Assignee: International Business Machines CorporationInventors: Binny S. Gill, Wendy A. Belluomini
-
Patent number: 8185754Abstract: The invention provides a method and system for time-based storage access, the method includes associating a plurality of storage volumes with specific periods of time during which they can be accessed, adjusting user fees based on access time periods of storage volumes, packing the plurality of storage volumes in available storage bins in the system based on periods of access for the plurality of storage volumes, wherein volumes with overlapping or similar periods of access are packed into a same storage bin if possible, and switching a storage bin to off or a reduced power state during periods when the storage volumes placed in the storage bin are not required, to reduce power consumption.Type: GrantFiled: February 25, 2009Date of Patent: May 22, 2012Assignee: International Business Machines CorporationInventors: Binny S. Gill, Madhukar R. Korupolu
-
Patent number: 8166463Abstract: A method and computer program product for code coverage utilizing efficient dynamic mutation of logic (EDML) are provided. A source code is read, and instrumentation points are located. Self Modifying Code (SMC) is inserted at the instrumentation points producing instrumented code. Additional functions are inserted in the source code to enable read and/or reset of code coverage statistics. The instrumented code is compiled, and executables are run for a period of time during which zero or more instrumentation points are executed. In response to executing instrumentation points, instructions are executed to record execution of the instrumented code. Instructions of the instrumented code overwrite themselves at certain points so that a next execution of the instrumentation points skips over the instrumented code at the certain points. Code coverage statistics are gathered and recorded. The code coverage statistics are reset to begin another period of time for gathering code coverage statistics.Type: GrantFiled: September 28, 2007Date of Patent: April 24, 2012Assignee: International Business Machines CorporationInventors: Binny S. Gill, Wendy A. Belluomini
-
Publication number: 20110320687Abstract: Embodiments of the invention are directed to reducing write amplification in a cache with flash memory used as a write cache. An embodiment of the invention includes partitioning at least one flash memory device in the cache into a plurality of logical partitions. Each of the plurality of logical partitions is a logical subdivision of one of the at least one flash memory device and comprises a plurality of memory pages. Data are buffered in a buffer. The data includes data to be cached, and data to be destaged from the cache to a storage subsystem. Data to be cached are written from the buffer to the at least one flash memory device. A processor coupled to the buffer is provided with access to the data written to the at least one flash memory device from the buffer, and a location of the data written to the at least one flash memory device within the plurality of logical partitions. The data written to the at least one flash memory device are destaged from the buffer to the storage subsystem.Type: ApplicationFiled: June 29, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wendy A. Belluomini, Binny S. Gill, Michael A. Ko
-
Publication number: 20110208941Abstract: A scalable, performance-based, volume allocation technique that can be applied in large storage controller collections is disclosed. A global resource tree of multiple nodes representing interconnected components of a storage system is analyzed to yield gap values for each node for a specific time period. The gap value for each node is an estimate of the amount of the additional or increased workload that can be allocated in the subtree of that node without exceeding the performance and space bounds at any of the nodes in that subtree for the specific time period. The gap values of the global resource tree are further analyzed to generate an ordered allocation list of the volumes of the storage system.Type: ApplicationFiled: February 22, 2010Publication date: August 25, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Binny S. Gill, Madhukar R. Korupolu
-
Publication number: 20110196987Abstract: Method, system, and computer program product embodiments for facilitating data compression are provided. A set of logical extents, each having compressed logical tracks of data, is mapped to a head physical extent and, if the head physical extent is determined to have been filled, to at least one overflow extent having spatial proximity to the head physical extent. Pursuant to at least one subsequent write operation and destage operation, the at least one subsequent write operation and destage operation determined to be associated with the head physical extent, the write operation is mapped to one of the head physical extent, the at least one overflow extent, and an additional extent having spatial proximity to the at least one overflow extent.Type: ApplicationFiled: February 5, 2010Publication date: August 11, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. BENHASE, Binny S. GILL, Lokesh M. GUPTA, Matthew J. KALOS, Gail A. SPEAR
-
Publication number: 20110093648Abstract: According to one embodiment, a method for using flash memory in a storage cache comprises receiving data to be cached in flash memory of a storage cache, at least some of the received data being received from at least one of a host system and a storage medium, selecting a block of the flash memory for receiving the data, buffering the received data until sufficient data has been received to fill the block, and overwriting existing data in the selected block with the buffered data. According to another embodiment, a method comprises receiving data, at least some of the data being from a host system and/or a storage medium, and sequentially overwriting sequential blocks of the flash memory with the received data. Other devices and methods for working with flash memory in a storage cache according to various embodiments are included and described herein.Type: ApplicationFiled: October 21, 2009Publication date: April 21, 2011Applicant: International Business Machines CorporationInventors: Wendy A. Belluomini, Binny S. Gill, Michael A. Ko
-
Publication number: 20100218013Abstract: The invention provides a method and system for time-based storage access, the method includes associating a plurality of storage volumes with specific periods of time during which they can be accessed, adjusting user fees based on access time periods of storage volumes, packing the plurality of storage volumes in available storage bins in the system based on periods of access for the plurality of storage volumes, wherein volumes with overlapping or similar periods of access are packed into a same storage bin if possible, and switching a storage bin to off or a reduced power state during periods when the storage volumes placed in the storage bin are not required, to reduce power consumption.Type: ApplicationFiled: February 25, 2009Publication date: August 26, 2010Applicant: International Business Machines CorporationInventors: Binny S. Gill, Madhukar R. Korupolu
-
Patent number: 7761664Abstract: Systems and methods for multi-level exclusive caching using hints. Exemplary embodiments include a method for multi-level exclusive caching, the method including identifying a cache management protocol within a multi-level cache hierarchy having a plurality of caches, defining a hint protocol within the multi-level cache hierarchy, identifying deciding caches and non-deciding caches within the multi-level cache hierarchy and implementing the hint protocol in conjunction with the cache management protocol to decide which pages within the multi-level cache to retain and where to store the pages.Type: GrantFiled: April 13, 2007Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventor: Binny S. Gill
-
Publication number: 20090089771Abstract: A method and computer program product for code coverage utilizing efficient dynamic mutation of logic (EDML) are provided. A source code is read, and instrumentation points are located. Self Modifying Code (SMC) is inserted at the instrumentation points producing instrumented code. Additional functions are inserted in the source code to enable read and/or reset of code coverage statistics. The instrumented code is compiled, and executables are run for a period of time during which zero or more instrumentation points are executed. In response to executing instrumentation points, instructions are executed to record execution of the instrumented code. Instructions of the instrumented code overwrite themselves at certain points so that a next execution of the instrumentation points skips over the instrumented code at the certain points. Code coverage statistics are gathered and recorded. The code coverage statistics are reset to begin another period of time for gathering code coverage statistics.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Binny S. Gill, Wendy A. Belluomini
-
Publication number: 20090089760Abstract: A computer program product for code coverage utilizing efficient dynamic mutation of logic (EDML) are provided. A source code is read, and instrumentation points are located. Self Modifying Code (SMC) is inserted at the instrumentation points producing instrumented code. Additional functions are inserted in the source code to enable read and/or reset of code coverage statistics. The instrumented code is compiled, and executables are run for a period of time during which zero or more instrumentation points are executed. In response to executing instrumentation points, instructions are executed to record execution of the instrumented code. Instructions of the instrumented code overwrite themselves at certain points so that a next execution of the instrumentation points skips over the instrumented code at the certain points. Code coverage statistics are gathered and recorded. The code coverage statistics are reset to begin another period of time for gathering code coverage statistics.Type: ApplicationFiled: March 28, 2008Publication date: April 2, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Binny S. Gill, Wendy A. Belluomini
-
Patent number: 7496714Abstract: A technique for determining when to destage write data from a fast, NVS of a computer system from an upper level to a lower level of storage in the computer system comprises adaptively varying a destage rate of the NVS according to a current storage occupancy of the NVS; maintaining a high threshold level for the NVS; maintaining a low threshold level that is set to be a predetermined fixed amount below the high threshold; setting the destage rate of the NVS to zero when the NVS occupancy is below the low threshold; setting the destage rate of the NVS to be maximum when the NVS occupancy is above the high threshold; linearly increasing the destage rate of the NVS from zero to maximum as the NVS occupancy goes from the low to the high threshold; and adaptively varying the high threshold in response to a dynamic computer storage workload.Type: GrantFiled: February 6, 2008Date of Patent: February 24, 2009Assignee: International Business Machines CorporationInventors: Binny S. Gill, Dharmendra S. Modha
-
Publication number: 20080256294Abstract: Systems and methods for multi-level exclusive caching using hints. Exemplary embodiments include a method for multi-level exclusive caching, the method including identifying a cache management protocol within a multi-level cache hierarchy having a plurality of caches, defining a hint protocol within the multi-level cache hierarchy, identifying deciding caches and non-deciding caches within the multi-level cache hierarchy and implementing the hint protocol in conjunction with the cache management protocol to decide which pages within the multi-level cache to retain and where to store the pages.Type: ApplicationFiled: April 13, 2007Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Binny S. Gill
-
Patent number: 7395377Abstract: A technique for determining when to destage write data from a fast, NVS of a computer system from an upper level to a lower level of storage in the computer system comprises adaptively varying a destage rate of the NVS according to a current storage occupancy of the NVS; maintaining a high threshold level for the NVS; maintaining a low threshold level that is set to be a predetermined fixed amount below the high threshold; setting the destage rate of the NVS to zero when the NVS occupancy is below the low threshold; setting the destage rate of the NVS to be maximum when the NVS occupancy is above the high threshold; linearly increasing the destage rate of the NVS from zero to maximum as the NVS occupancy goes from the low to the high threshold; and adaptively varying the high threshold in response to a dynamic computer storage workload.Type: GrantFiled: April 20, 2006Date of Patent: July 1, 2008Assignee: International Business Machines CorporationInventors: Binny S. Gill, Dharmendra S. Modha
-
Publication number: 20080126708Abstract: A technique for determining when to destage write data from a fast, NVS of a computer system from an upper level to a lower level of storage in the computer system comprises adaptively varying a destage rate of the NVS according to a current storage occupancy of the NVS; maintaining a high threshold level for the NVS; maintaining a low threshold level that is set to be a predetermined fixed amount below the high threshold; setting the destage rate of the NVS to zero when the NVS occupancy is below the low threshold; setting the destage rate of the NVS to be maximum when the NVS occupancy is above the high threshold; linearly increasing the destage rate of the NVS from zero to maximum as the NVS occupancy goes from the low to the high threshold; and adaptively varying the high threshold in response to a dynamic computer storage workload.Type: ApplicationFiled: February 6, 2008Publication date: May 29, 2008Applicant: International Business Machines CorporationInventors: Binny S. Gill, Dharmendra S. Modha
-
Patent number: 7260679Abstract: A method is disclosed to manage a data cache. The method provides a data cache comprising a plurality of tracks, where each track comprises one or more segments. The method further maintains a first LRU list comprising one or more first tracks having a low reuse potential, maintains a second LRU list comprising one or more second tracks having a high reuse potential, and sets a target size for the first LRU list. The method then accesses a track, and determines if that accessed track comprises a first track. If the method determines that the accessed track comprises a first track, then the method increases the target size for said first LRU list. Alternatively, if the method determines that the accessed track comprises a second track, then the method decreases the target size for said first LRU list. The method demotes tracks from the first LRU list if its size exceeds the target size; otherwise, the method evicts tracks from the second LRU list.Type: GrantFiled: October 12, 2004Date of Patent: August 21, 2007Assignee: International Business Machines CorporationInventors: Michael T. Benhase, Binny S. Gill, Thomas C. Jarvis, Dharmendra S. Modha