Abstract: Technology for reading memory cells in three-dimensional memory having multiple tiers. The memory system erases the tiers within each block independently. Then, memory cells in the tiers are programmed by units such as word lines. The memory system determines one or more read parameters for the selected tier based on the programmed/erased states of the other tiers in the block. For example, the memory system may select read reference levels for the selected tier based on the programmed/erased states of the other tiers. In an aspect, the one or more read parameters are used to determine the set of reference voltages for a bit error rate estimation scan (BES).

Abstract: Techniques are presented that allow for the erase of the drain side select gates of NAND strings while maintaining the data content of the memory cells. While erase inhibiting the memory cells of a NAND string, holes are generated in the drain region through the gate induced drain leakage (GIDL) mechanism and transferred to under the select gate, where they are then used to erase the select gate by Fowler-Nordheim mechanism. This allows for the refresh of the drain side select gates while retaining the data content of the NAND strings. This technique can also be used for data encryption, since, by erasing the drain side select gates, a block of data can be rendered unreadable; but, since the data content is not erased, it can later be recovered.

Abstract: Embodiments of the disclosed technology relate to the operation of memory devices, and more particularly to sub-block mode (SBM) pre-charge operation sequences. One example embodiment provides a novel logic design of the control circuitry of a memory device using comments/instructions for the control circuitry. By virtue of the features of the disclosed technology, the control circuitry can effect pre-charging of an inner or middle vertical sub-block of a NAND string in a memory array. In some examples the NAND string has at least three vertical sub-blocks of non-volatile memory cells.

Abstract: A three tier memory has an upper sub block, a lower sub block, and a middle sub block. In the present disclosure, rather than precharging the upper and lower sub blocks, use is made of the middle sub block using a firmware (FW) scheme. Upon receiving a write request from a host, the FW will route the data to the middle sub block (SB1) through reverse order programming (ROP) so that the SB1 is pre-charged through the source side through the lower sub block (SB0). Once the SB1 is written, data is then routed to the SBO and then to the upper sub block (SB2). When there is a garbage collection (GC) request, the FW will move the data from the SB2 and then erase the SB2. Then the data moves from the SBO and SBO is erased. Finally, the data moves from the SB1 and then SB1 is erased.

Abstract: A measurement circuit may include a transistor having a first terminal, a second terminal, and a third terminal, wherein the first terminal is coupled to a first reference voltage. The measurement circuit may further include a first operational amplifier including a first input coupled to the second terminal of the transistor and an output coupled to the third terminal of the transistor. The first operational amplifier may further include a second input configured to receive a second reference voltage. The measurement circuit may also include a first unity-gain voltage follower including a second operational amplifier having a first input coupled to the first input of the first operational amplifier. Methods of measuring a threshold voltage, semiconductor devices, and electronic systems are also described.

Abstract: A measurement circuit may include a transistor having a first terminal, a second terminal, and a third terminal, wherein the first terminal is coupled to a first reference voltage. The measurement circuit may further include a first operational amplifier including a first input coupled to the second terminal of the transistor and an output coupled to the third terminal of the transistor. The first operational amplifier may further include a second input configured to receive a second reference voltage. The measurement circuit may also include a first unity-gain voltage follower including a second operational amplifier having a first input coupled to the first input of the first operational amplifier. Methods of measuring a threshold voltage, semiconductor devices, and electronic systems are also described.