Abstract: Described herein are wavelength division multiplexing (WDM) transceivers configured to support fast, bidirectional communication over optical channels. An optical transceiver comprises a transmitter, a receiver, an input/output (I/O) port and an optical interleaver. The transmitter comprises a first bus waveguide and a plurality of optical modulators coupled to the first bus waveguide, each of the optical modulators being resonant at a respective wavelengths in a first wavelength set. The receiver comprises a second bus waveguide and a plurality of optical filters coupled to the second bus waveguide, each of the optical filters being resonant at a respective wavelength in a second wavelength set. The (I/O) port is coupled to an optical channel.

Abstract: Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

Abstract: Described herein are wavelength division multiplexing (WDM) transceivers configured to support fast, bidirectional communication over optical channels. An optical transceiver comprises a transmitter, a receiver, an input/output (I/O) port and an optical interleaver. The transmitter comprises a first bus waveguide and a plurality of optical modulators coupled to the first bus waveguide, each of the optical modulators being resonant at a respective wavelengths in a first wavelength set. The receiver comprises a second bus waveguide and a plurality of optical filters coupled to the second bus waveguide, each of the optical filters being resonant at a respective wavelength in a second wavelength set. The (I/O) port is coupled to an optical channel.

Abstract: Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

Abstract: Provided herein are optical fiber arrays and optical assemblies included optical fiber arrays. The optical fiber array includes a fiber array chip that has first optical connections disposed on a first edge of the fiber array chip and second optical connections disposed on a second edge of the fiber array chip. Optical fibers are coupled to the first optical connections. Active devices (e.g., photonic and/or electronic devices) are disposed on the fiber array chip. The optical fiber array is removably, optically couplable to another optical component such as a photonic integrated circuit.

Abstract: Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

Abstract: There is set forth herein a semiconductor assembly including an integrated circuit and a set of springs extending from the integrated circuit that can be adapted for connection to an external article. The external article can be e.g. an integrated circuit or a printed circuit board. On connection of the semiconductor assembly to an external article there can be defined a semiconductor assembly comprising the integrated circuit the set of springs and the external article. The set of springs can be metal nanospring array can formed by GLAD (Glancing angle deposition) process. In one embodiment, the nanospring array can be GLAD formed on a substrate and then applied to the integrated circuit. In one embodiment, the nanospring array can be GLAD formed on the integrated circuit.

Abstract: The present invention provides for a method of monitoring the concentration of a sulfate salt present in a solution. In accordance with this aspect of the present invention, the concentration of sulfate salt present in the solution is monitored by titrating a known concentration of a barium salt solution with a test sample of the solution containing an unknown amount of sulfate salt under conductivity titration conditions.