Patents by Inventor BINU JOHN

BINU JOHN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11921558
    Abstract: In one embodiment, a processor includes: a plurality of cores to execute instructions; a power controller to control power consumption of the plurality of cores, the power controller to receive network traffic metadata from a classifier and control the power consumption of at least one of the plurality of cores based at least in part on the network traffic metadata; and a hardware feedback circuit coupled to the plurality of cores, the hardware feedback circuit to determine hardware feedback information comprising an energy efficiency capability and a performance capability of at least some of the plurality of cores based at least in part on the network traffic metadata. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Venkateshan Udhayan, Sravan Akepati, Ashraf H. Wadaa, Shahrnaz Azizi, Kristoffer Fleming, Ajay Gupta, Binu John
  • Publication number: 20220011852
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to align network traffic to improve power consumption. Example instructions cause one or more processors to classify a workload based on network packets obtained via a wireless communication; determine heuristics of platform activities corresponding to the workload; and schedule network interrupts based on hardware-based wake interrupts from a sleep mode using the heuristics.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Inventors: Venkateshan Udhayan, Sravan Akepati, Shahrnaz Azizi, Ajay Gupta, Binu John, Bharath Prabhu Perdoor, Leor Rom, Ashraf H Wadaa, Alexander Min
  • Publication number: 20220004354
    Abstract: Example apparatus disclosed herein compare one or more audio latency characteristics with one or more audio latency requirements in response to detection of an audio silence event, the audio latency characteristic(s) associated with at least one of a hardware layer or a device layer of an audio stack of a compute device, the audio latency requirement(s) associated with an application. Disclosed example apparatus also control a device layer of the audio stack to enter a device layer low power mode in response to a first determination that the audio latency requirement(s) is/are met by the audio latency characteristic(s). Disclosed example apparatus further control a hardware layer of the audio stack to enter a hardware layer low power mode in response to the first determination and a second determination that an operation condition for entry into the hardware layer low power mode is met.
    Type: Application
    Filed: September 22, 2021
    Publication date: January 6, 2022
    Inventors: Aruni Nelson, Adeel Aslam, Abdul Ismail, Devon Worrell, Binu John
  • Publication number: 20190164357
    Abstract: Determining toll data can include receiving a first data set, wherein the first data set corresponds to one or more toll stations, and receiving a second data set indicating either or both lane and traffic information associated with at least one of the toll stations, the first data set being processed to determine at least one payment option associated with the one or more toll stations, wherein the at least one payment option is output to a human machine interface for selection by a user of a vehicle. A toll station lane of a first toll station can be allocated based on the second data set. The allocated toll station lane can be output to a human machine interface to guide the user.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 30, 2019
    Inventor: BINU JOHN
  • Publication number: 20110004703
    Abstract: A circuit for handling an illegal command embodies a control decode stage, illegal command handling stage and an output stage. The control decode circuit receives a clock signal, receives and decodes an external command, and latches the decoded external command based on the clock signal to generate a first signal. The first device is coupled to the control decode circuit for receiving the first signal, receives a second signal indicating whether the illegal command is detected in the external command, and generates a third signal based on the first and the second signals. The output circuit is coupled to the first device, receives the clock signal and the third signal, and generates a first output based on the clock signal and the third signal. If there is an illegal command, then there will be no control output generated. On the other hand, in the absence of an illegal command a control output will be generated.
    Type: Application
    Filed: July 2, 2009
    Publication date: January 6, 2011
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Ibrahim MURTUZA, Binu John BABU