Patents by Inventor Binuraj Ravindran

Binuraj Ravindran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10672393
    Abstract: A system, apparatus, method, and computer program product for a speaking aid. The system including network interface circuitry to receive speech input from a user. The speech input includes a partial sentence with a missing word or the partial sentence with a stuttered word. The system also includes a processor coupled to the network interface circuitry and one or more memory devices coupled to the processor. The one or more memory devices include instructions, that when executed by the processor, cause the system to detect a stutter or pause in the speech input, predict the stuttered word or the missing word, present a predicted word from an n-best list to the user; and if a prompt is received from the user, present a next word from the n-best list until the user speaks a correct word to replace the stutter or the pause.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Ze'ev Rivlin, Vered Bar Bracha, Douglas Gabel, Jonathan Huang, Sylvia Downing, Binuraj Ravindran, Willem Beltman
  • Patent number: 10614811
    Abstract: A system, method, apparatus and computer readable medium for hierarchical speech recognition resolution. The method of hierarchical speech recognition resolution on a platform includes receiving a speech stream from a microphone. The speech stream is resolved using a lowest possible level automatic speech recognition (ASR) engine of multi-level ASR engines. The selection of the lowest possible level ASR engine is based on policies defined for the platform. If resolution of the speech stream is rated less than a predetermined confidence level, the resolution of the speech stream is pushed to a next higher-level ASR engine of the multi-level ASR engines until the resolution of the speech stream meets the predetermined confidence level without violating one or more policies.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Douglas Gabel, Jonathan Huang, Sylvia J. Downing, Narayan Biswal, Binuraj Ravindran, Willem Beltman, Vered Bar Bracha, Ze'Ev Rivlin
  • Patent number: 10403266
    Abstract: An example apparatus for detecting keywords in audio includes an audio receiver to receive audio comprising a keyword to be detected. The apparatus also includes a spike transducer to convert the audio into a plurality of spikes. The apparatus further includes a spiking neural network to receive one or more of the spikes and generate a spike corresponding to a detected keyword.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Muhammad Khellah, Oren Arad, Binuraj Ravindran, Somnath Paul, Charles Augustine, Bruno Umbria Pedroni
  • Publication number: 20190115011
    Abstract: An example apparatus for detecting keywords in audio includes an audio receiver to receive audio comprising a keyword to be detected. The apparatus also includes a spike transducer to convert the audio into a plurality of spikes. The apparatus further includes a spiking neural network to receive one or more of the spikes and generate a spike corresponding to a detected keyword.
    Type: Application
    Filed: October 18, 2017
    Publication date: April 18, 2019
    Applicant: Intel Corporation
    Inventors: Muhammad Khellah, Oren Arad, Binuraj Ravindran, Somnath Paul, Charles Augustine, Bruno Umbria Pedroni
  • Publication number: 20190043490
    Abstract: A system, apparatus, method, and computer program product for a speaking aid. The system including network interface circuitry to receive speech input from a user. The speech input includes a partial sentence with a missing word or the partial sentence with a stuttered word. The system also includes a processor coupled to the network interface circuitry and one or more memory devices coupled to the processor. The one or more memory devices include instructions, that when executed by the processor, cause the system to detect a stutter or pause in the speech input, predict the stuttered word or the missing word, present a predicted word from an n-best list to the user; and if a prompt is received from the user, present a next word from the n-best list until the user speaks a correct word to replace the stutter or the pause.
    Type: Application
    Filed: January 12, 2018
    Publication date: February 7, 2019
    Inventors: Ze'ev Rivlin, Vered Bar Bracha, Douglas Gabel, Jonathan Huang, Sylvia Downing, Binuraj Ravindran, Willem Beltman
  • Publication number: 20190043525
    Abstract: A system, apparatus, method, and computer readable medium for using an audio trigger for surveillance in a security system. The method including receiving an audio input stream via a microphone. Dividing the audio input stream into audio segments. Filtering high energy audio segments from the audio segments. If a high energy audio segment includes speech, then determining if the speech is recognized as the speech of users of the system. If the high energy audio segment does not include the speech, then classifying the high energy audio segment as an interesting sound or an uninteresting sound. Determining whether to turn video on based on classification of the high energy audio segment as the interesting sound, speech recognition of the speech as the speech of the users of the system, and contextual data.
    Type: Application
    Filed: January 12, 2018
    Publication date: February 7, 2019
    Inventors: Jonathan Huang, Willem Beltman, Vered Bar Bracha, Ze'ev Rivlin, Douglas Gabel, Sylvia Downing, Narayan Biswal, Binuraj Ravindran
  • Publication number: 20190035404
    Abstract: A system, method, apparatus and computer readable medium for hierarchical speech recognition resolution. The method of hierarchical speech recognition resolution on a platform includes receiving a speech stream from a microphone. The speech stream is resolved using a lowest possible level automatic speech recognition (ASR) engine of multi-level ASR engines. The selection of the lowest possible level ASR engine is based on policies defined for the platform. If resolution of the speech stream is rated less than a predetermined confidence level, the resolution of the speech stream is pushed to a next higher-level ASR engine of the multi-level ASR engines until the resolution of the speech stream meets the predetermined confidence level without violating one or more policies.
    Type: Application
    Filed: December 29, 2017
    Publication date: January 31, 2019
    Inventors: Douglas Gabel, Jonathan Huang, Sylvia J. Downing, Narayan Biswal, Binuraj Ravindran, Willem Beltman, Vered Bar Bracha, Ze'Ev Rivlin
  • Patent number: 9536535
    Abstract: Described herein are systems, methods and apparatus for decoding in-band on-channel signals and extracting audio and data signals. Memory requirements are reduced by selectively filtering a bit stream of data in the signal so that services of interest which are encoded therein are processed. A single pool of memory may be shared between physical layer and data link layer processing. Memory in this pool may be allocated dynamically between processing of data at the physical and data link layers. When the available memory is not sufficient to support the required services, the dynamic allocation allows for graceful degradation.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: January 3, 2017
    Assignee: Intel IP Corporation
    Inventors: Dongsheng Bi, Binuraj Ravindran, Bassel Haddad
  • Publication number: 20160284349
    Abstract: A system, article, and method of environment-sensitive automatic speech recognition.
    Type: Application
    Filed: March 26, 2015
    Publication date: September 29, 2016
    Inventors: Binuraj Ravindran, Georg Stemmer, Joachim Hofer
  • Patent number: 8589634
    Abstract: Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerate SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: November 19, 2013
    Assignee: SiPort, Inc.
    Inventors: Sridhar G. Sharma, Binuraj Ravindran, Jeffrey V. Hill
  • Publication number: 20120265329
    Abstract: Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerate SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.
    Type: Application
    Filed: May 25, 2012
    Publication date: October 18, 2012
    Inventors: Sridhar G. SHARMA, Binuraj RAVINDRAN, Jeffrey V. HILL
  • Publication number: 20120016502
    Abstract: Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerate SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.
    Type: Application
    Filed: July 26, 2011
    Publication date: January 19, 2012
    Inventors: Sridhar G. Sharma, Binuraj Ravindran, Jeffrey V. Hill
  • Patent number: 8015368
    Abstract: Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerat SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: September 6, 2011
    Assignee: Siport, Inc.
    Inventors: Sridhar Sharma, Binuraj Ravindran, Jeffrey V. Hill
  • Publication number: 20080263285
    Abstract: Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerat SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.
    Type: Application
    Filed: April 21, 2008
    Publication date: October 23, 2008
    Inventors: Sridhar Sharma, Binuraj Ravindran, Jeffrey V. Hill