Patents by Inventor Bi-O KIM
Bi-O KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10453707Abstract: A method for fabricating a semiconductor device, the method including forming a mold structure on a substrate such that the mold structure includes alternately and repeatedly stacked interlayer insulating films and sacrificial films; forming a channel hole passing through the mold structure; forming a vertical channel structure within the channel hole; exposing a surface of the interlayer insulating films by removing the sacrificial films; forming an aluminum oxide film along a surface of the interlayer insulating films; forming a continuous film on the aluminum oxide film; and nitriding the continuous film to form a TiN film.Type: GrantFiled: October 24, 2017Date of Patent: October 22, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Seok Cho, Hyung Joon Kim, Jung Ho Kim, Joong Yun Ra, Bi O Kim, Jae Young Ahn, Ki Yong Oh, Sung Hae Lee
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Publication number: 20180315621Abstract: A method for fabricating a semiconductor device, the method including forming a mold structure on a substrate such that the mold structure includes alternately and repeatedly stacked interlayer insulating films and sacrificial films; forming a channel hole passing through the mold structure; forming a vertical channel structure within the channel hole; exposing a surface of the interlayer insulating films by removing the sacrificial films; forming an aluminum oxide film along a surface of the interlayer insulating films; forming a continuous film on the aluminum oxide film; and nitriding the continuous film to form a TiN film.Type: ApplicationFiled: October 24, 2017Publication date: November 1, 2018Inventors: Yong Seok CHO, Hyung Joon KIM, Jung Ho KIM, Joong Yun RA, Bi O KIM, Jae Young AHN, Ki Yong OH, Sung Hae LEE
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Patent number: 9698233Abstract: Tunnel insulation layer structures and methods of manufacturing the same are disclosed. The tunnel insulation layer structures may include a first tunnel insulation layer, a second tunnel insulation layer, a third tunnel insulation layer, a fourth tunnel insulation layer and a fifth tunnel insulation layer. The first tunnel insulation layer on a substrate has a first band gap energy. The second tunnel insulation layer on the first tunnel insulation layer has a second band gap energy which is lower than the first band gap energy. The third tunnel insulation layer on the second tunnel insulation layer has a third band gap energy which is higher than the second band gap energy. The fourth tunnel insulation layer on the third tunnel insulation layer has a fourth band gap energy which is lower than the third band gap energy. The fifth tunnel insulation layer on the fourth tunnel insulation layer has a fifth band gap energy which is higher than the fourth band gap energy.Type: GrantFiled: March 11, 2015Date of Patent: July 4, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Yeoung Choi, Young-Jin Noh, Bi-O Kim, Kwang-Min Park, Jae-Young Ahn, Ju-Mi Yun, Jae-Ho Choi, Ki-Hyun Hwang
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Patent number: 9530899Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes insulation layers and gate electrodes alternately stacked on a substrate, a vertical channel vertically passing through the insulation layers and the gate electrodes, and a threshold voltage controlling insulation layer, a tunnel insulation layer and a charge storage layer disposed between the vertical channel and the gate electrodes, wherein the threshold voltage controlling insulation layer is disposed between the charge storage layer and the vertical channel and including a material configured to suppress an inversion layer from being formed in the vertical channel.Type: GrantFiled: September 2, 2014Date of Patent: December 27, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Bi O Kim, Jin-Tae Noh, Su-Jin Shin, Jae-Young Ahn, Ki-Hyun Hwang
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Patent number: 9343546Abstract: A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer.Type: GrantFiled: October 3, 2014Date of Patent: May 17, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Bi-o Kim, Jin-tae Noh, Chang-woo Sun, Jae-young Ahn, Seung-hyun Lim, Ki-hyun Hwang
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Patent number: 9324730Abstract: A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.Type: GrantFiled: January 21, 2015Date of Patent: April 26, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Phil-Ouk Nam, Dong-Chul Yoo, Bi-O Kim, Jae-Young Ahn, Byong-Hyun Jang, Ki-Hyun Hwang
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Publication number: 20150279955Abstract: Tunnel insulation layer structures and methods of manufacturing the same are disclosed. The tunnel insulation layer structures may include a first tunnel insulation layer, a second tunnel insulation layer, a third tunnel insulation layer, a fourth tunnel insulation layer and a fifth tunnel insulation layer. The first tunnel insulation layer on a substrate has a first band gap energy. The second tunnel insulation layer on the first tunnel insulation layer has a second band gap energy which is lower than the first band gap energy. The third tunnel insulation layer on the second tunnel insulation layer has a third band gap energy which is higher than the second band gap energy. The fourth tunnel insulation layer on the third tunnel insulation layer has a fourth band gap energy which is lower than the third band gap energy. The fifth tunnel insulation layer on the fourth tunnel insulation layer has a fifth band gap energy which is higher than the fourth band gap energy.Type: ApplicationFiled: March 11, 2015Publication date: October 1, 2015Inventors: Eun-Yeoung CHOI, Young-Jin NOH, Bi-O KIM, Kwang-Min PARK, Jae-Young AHN, Ju-Mi YUN, Jae-Ho CHOI, Ki-Hyun HWANG
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Patent number: 9129857Abstract: According to example embodiments, a semiconductor device includes horizontal patterns stacked on a substrate. The horizontal patterns define an opening through the horizontal patterns. A first core pattern is in the opening. A second core pattern is in the opening on the first core pattern. A first active pattern is between the first core pattern and the horizontal patterns. A second active pattern containing a first element is between the second core pattern and the horizontal patterns. The second active pattern contains the first element at a higher concentration than a concentration of the first element in the second core pattern.Type: GrantFiled: July 27, 2012Date of Patent: September 8, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Bi-O Kim, Byong-Ju Kim, Jung-Geun Jee, Jin-Gyun Kim, Jae-Young Ahn, Ki-Hyun Hwang
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Publication number: 20150206900Abstract: A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.Type: ApplicationFiled: January 21, 2015Publication date: July 23, 2015Inventors: Phil-Ouk NAM, Dong-Chul YOO, Bi-O KIM, Jae-Young AHN, Byong-Hyun JANG, Ki-Hyun HWANG
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Patent number: 9064895Abstract: Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.Type: GrantFiled: July 17, 2013Date of Patent: June 23, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Bi-O Kim, Toshiro Nakanishi, Jin-Tae Noh, Chang-Woo Sun, Seung-Hyun Lim, Jae-Young Ahn, Ki-Hyun Hwang
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Publication number: 20150129954Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes insulation layers and gate electrodes alternately stacked on a substrate, a vertical channel vertically passing through the insulation layers and the gate electrodes, and a threshold voltage controlling insulation layer, a tunnel insulation layer and a charge storage layer disposed between the vertical channel and the gate electrodes, wherein the threshold voltage controlling insulation layer is disposed between the charge storage layer and the vertical channel and including a material configured to suppress an inversion layer from being formed in the vertical channel.Type: ApplicationFiled: September 2, 2014Publication date: May 14, 2015Inventors: Bi O. Kim, Jin-Tae Noh, Su-Jin Shin, Jae-Young Ahn, Ki-Hyun Hwang
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Publication number: 20150056797Abstract: A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer.Type: ApplicationFiled: October 3, 2014Publication date: February 26, 2015Inventors: Bi-o Kim, Jin-tae Noh, Chang-woo Sun, Jae-young Ahn, Seung-hyun Lim, Ki-hyun Hwang
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Patent number: 8901643Abstract: A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer.Type: GrantFiled: March 12, 2013Date of Patent: December 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Bi-o Kim, Jin-tae Noh, Chang-woo Sun, Jae-young Ahn, Seung-hyun Lim, Ki-hyun Hwang
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Publication number: 20140024189Abstract: Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.Type: ApplicationFiled: July 17, 2013Publication date: January 23, 2014Inventors: Bi-O Kim, Toshiro Nakanishi, Jin-Tae Noh, Chang-Woo Sun, Seung-Hyun Lim, Jae-Young Ahn, Ki-Hyun Hwang
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Patent number: 8617947Abstract: A method of manufacturing a semiconductor device includes forming a channel region, forming a buffer layer on the channel region, and heat-treating the channel region by using a gas containing halogen atoms.Type: GrantFiled: April 26, 2012Date of Patent: December 31, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-kyu Yang, Phil-ouk Nam, Ki-hyun Hwang, Jae-young Ahn, Han-mei Choi, Bi-o Kim
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Publication number: 20130270631Abstract: A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer.Type: ApplicationFiled: March 12, 2013Publication date: October 17, 2013Inventors: Bi-o KIM, Jin-tae NOH, Chang-woo SUN, Jae-young AHN, Seung-hyun LIM, Ki-hyun HWANG
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Publication number: 20130032878Abstract: According to example embodiments, a semiconductor device includes horizontal patterns stacked on a substrate. The horizontal patterns define an opening through the horizontal patterns. A first core pattern is in the opening. A second core pattern is in the opening on the first core pattern. A first active pattern is between the first core pattern and the horizontal patterns. A second active pattern containing a first element is between the second core pattern and the horizontal patterns. The second active pattern contains the first element at a higher concentration than a concentration of the first element in the second core pattern.Type: ApplicationFiled: July 27, 2012Publication date: February 7, 2013Inventors: Bi-O Kim, Byong-Ju Kim, Jung-Geun Jee, Jin-Gyun Kim, Jae-Young Ahn, Ki-Hyun Hwang
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Publication number: 20120276702Abstract: A method of manufacturing a semiconductor device includes forming a channel region, forming a buffer layer on the channel region, and heat-treating the channel region by using a gas containing halogen atoms.Type: ApplicationFiled: April 26, 2012Publication date: November 1, 2012Inventors: Jun-kyu YANG, Phil-ouk Nam, Ki-hyun Hwang, Jae-young Ahn, Han-mei Choi, Bi-o Kim
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Publication number: 20080305572Abstract: There are provided a method of fabricating an image device having a capacitor and an image device fabricated thereby. The method comprises preparing a substrate having a pixel region and a peripheral circuit region. A lower electrode containing silicon is formed on the substrate of the peripheral circuit region. A capacitor dielectric layer is formed by sequentially stacking a first dielectric layer and a second dielectric layer on the lower electrode, and the first dielectric layer and the second dielectric layer have a different dielectric constant from each other. In this case, one of the first and second dielectric layers is a dielectric layer grown from a material layer formed thereunder and has a lower dielectric constant than that of the other. An upper electrode is formed on the capacitor dielectric layer.Type: ApplicationFiled: June 3, 2008Publication date: December 11, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Sub YOU, Dae-Han YOO, Yong-Woo HYUNG, Jae-Jong HAN, Bi-O KIM, Gil-Hwan SON