Patents by Inventor Biow-Hiem Ong

Biow-Hiem Ong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240321741
    Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers. Each of the tiers individually comprise a conductive structure and an insulative structure. The microelectronic device comprises a staircase structure having steps comprising lateral ends of the tiers, and contacts overlying the steps at different elevations of the staircase structure. The contacts comprise a liner material. The microelectronic device comprises conductive plug structures underlying the liner material of the contacts and comprising lateral portions within voids in at least some of the conductive structures, and vertical portions overlying the lateral portions. Related electronic systems and methods are also described.
    Type: Application
    Filed: January 30, 2024
    Publication date: September 26, 2024
    Inventors: Zhou Xuan, Sijia Yu, Biow Hiem Ong
  • Publication number: 20240274538
    Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
    Type: Application
    Filed: April 22, 2024
    Publication date: August 15, 2024
    Inventors: Biow Hiem Ong, David A. Daycock, Chieh Hsien Quek, Chii Wean Calvin Chen, Christian George Emor, Wing Yu Lo
  • Publication number: 20240266214
    Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.
    Type: Application
    Filed: April 19, 2024
    Publication date: August 8, 2024
    Inventors: Xiaosong Zhang, Yongjun J. Hu, David A. Kewley, Md Zahid Hossain, Michael J. Irwin, Daniel Billingsley, Suresh Ramarajan, Robert J. Hanson, Biow Hiem Ong, Keen Wah Chow
  • Patent number: 11990367
    Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: May 21, 2024
    Inventors: Xiaosong Zhang, Yongjun J. Hu, David A. Kewley, Md Zahid Hossain, Michael J. Irwin, Daniel Billingsley, Suresh Ramarajan, Robert J. Hanson, Biow Hiem Ong, Keen Wah Chow
  • Patent number: 11967556
    Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: April 23, 2024
    Inventors: Biow Hiem Ong, David A. Daycock, Chieh Hsien Quek, Chii Wean Calvin Chen, Christian George Emor, Wing Yu Lo
  • Publication number: 20230063178
    Abstract: A microelectronic device includes a stack structure including a vertically alternating sequence of conductive structures and insulating structures arranged in tiers, a dielectric-filled opening vertically extending into the stack structure and defined between two internal sidewalls of the stack structure, a stadium structure within the stack structure and comprising steps defined by horizontal ends of at least some of the tiers, a first ledge extending upward from a first uppermost step of the steps of the stadium structure and interfacing with a first internal sidewall of the two internal sidewalls of the stack structure, and a second ledge extending upward from a second, opposite uppermost step of the steps of the stadium structure and interfacing with a second, opposite internal sidewall of the two internal sidewalls.
    Type: Application
    Filed: December 29, 2021
    Publication date: March 2, 2023
    Inventors: Bo Zhao, Matthew J. King, Jason Reece, Michael J. Gossman, Shruthi Kumara Vadivel, Martin J. Barclay, Lifang Xu, Joel D. Peterson, Matthew Park, Adam L. Olson, David A. Kewley, Xiaosong Zhang, Justin B. Dorhout, Zhen Feng Yow, Kah Sing Chooi, Tien Minh Quan Tran, Biow Hiem Ong
  • Publication number: 20220045007
    Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
    Type: Application
    Filed: October 25, 2021
    Publication date: February 10, 2022
    Inventors: Biow Hiem Ong, David A. Daycock, Chieh Hsien Quek, Chii Wean Calvin Chen, Christian George Emor, Wing Yu Lo
  • Publication number: 20210375670
    Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.
    Type: Application
    Filed: August 12, 2021
    Publication date: December 2, 2021
    Inventors: Xiaosong Zhang, Yongjun J. Hu, David A. Kewley, Md Zahid Hossain, Michael J. Irwin, Daniel Billingsley, Suresh Ramarajan, Robert J. Hanson, Biow Hiem Ong, Keen Wah Chow
  • Patent number: 11158577
    Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Biow Hiem Ong, David A. Daycock, Chieh Hsien Quek, Chii Wean Calvin Chen, Christian George Emor, Wing Yu Lo
  • Patent number: 11101171
    Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Xiaosong Zhang, Yongjun J. Hu, David A. Kewley, Md Zahid Hossain, Michael J. Irwin, Daniel Billingsley, Suresh Ramarajan, Robert J. Hanson, Biow Hiem Ong, Keen Wah Chow
  • Publication number: 20210242131
    Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 5, 2021
    Inventors: Biow Hiem Ong, David A. Daycock, Chieh Hsien Quek, Chii Wean Calvin Chen, Christian George Emor, Wing Yu Lo
  • Publication number: 20210050252
    Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.
    Type: Application
    Filed: August 16, 2019
    Publication date: February 18, 2021
    Inventors: Xiaosong Zhang, Yongjun J. Hu, David A. Kewley, Md Zahid Hossain, Michael J. Irwin, Daniel Billingsley, Suresh Ramarajan, Robert J. Hanson, Biow Hiem Ong, Keen Wah Chow
  • Patent number: 9689805
    Abstract: A method for inspecting a manufactured product includes applying a first test regimen to the manufactured product to identify product defects. The first test regimen produces a first set of defect candidates. The method further includes applying a second test regimen to the manufactured product to identify product defects. The second test regimen produces a second set of defect candidates, and the second test regimen is different from the first test regimen. The method also includes generating a first filtered defect set by eliminating ones of the first set of defect candidates that are not identified in the second set of defect candidates.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: June 27, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Biow-Hiem Ong, Chih-Chiang Tu, Chien-Hung Lai, Jong-Yuh Chang, Kuang-Yu Liu
  • Publication number: 20150316489
    Abstract: A method for inspecting a manufactured product includes applying a first test regimen to the manufactured product to identify product defects. The first test regimen produces a first set of defect candidates. The method further includes applying a second test regimen to the manufactured product to identify product defects. The second test regimen produces a second set of defect candidates, and the second test regimen is different from the first test regimen. The method also includes generating a first filtered defect set by eliminating ones of the first set of defect candidates that are not indentified in the second set of defect candidates.
    Type: Application
    Filed: June 23, 2015
    Publication date: November 5, 2015
    Inventors: Biow-Hiem Ong, CHIH-CHIANG TU, Chien-Hung Lai, JONG-YUH CHANG, Kuang-Yu Liu
  • Patent number: 9063097
    Abstract: A method for inspecting a manufactured product includes applying a first test regimen to the manufactured product to identify product defects. The first test regimen produces a first set of defect candidates. The method further includes applying a second test regimen to the manufactured product to identify product defects. The second test regimen produces a second set of defect candidates, and the second test regimen is different from the first test regimen. The method also includes generating a first filtered defect set by eliminating ones of the first set of defect candidates that are not indentified in the second set of defect candidates.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: June 23, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Biow-Hiem Ong, Chien-Hung Lai, Chih-Chiang Tu, Jong-Yuh Chang, Kuang-Yu Liu
  • Patent number: 8818072
    Abstract: The present disclosure provides a method of inspecting a photolithographic mask wherein a design database is received, and a feature of the design database is adjusted by a bias factor to produce a biased database. Image rendering is performed on the biased database to produce a biased image. A mask is also created using the design database, and the mask is imaged to produce a mask image. The biased image is compared to the mask image, and a new value for the bias factor may be determined based on the comparison.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Biow-Hiem Ong, Rick Lai, Chih-Chiang Tu, Chia-Shih Lin, Jong-Yuh Chang
  • Patent number: 8629407
    Abstract: A method of forming a standard mask for an inspection system is provided, the method comprising providing a substrate within a chamber, and providing a tetraethylorthosilicate (TEOS) precursor within the chamber. The method further includes reacting the TEOS precursor with an electron beam to form silicon oxide particles of controlled size at one or more controlled locations on the substrate, the silicon oxide particles disposed as simulated contamination defects.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hung Lai, Biow-Hiem Ong, Chia-Shih Lin, Jong-Yuh Chang, Chih-Chiang Tu
  • Publication number: 20120261563
    Abstract: A method of forming a standard mask for an inspection system is provided, the method comprising providing a substrate within a chamber, and providing a tetraethylorthosilicate (TEOS) precursor within the chamber. The method further includes reacting the TEOS precursor with an electron beam to form silicon oxide particles of controlled size at one or more controlled locations on the substrate, the silicon oxide particles disposed as simulated contamination defects.
    Type: Application
    Filed: April 13, 2011
    Publication date: October 18, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hung Lai, Biow-Hiem Ong, Chia-Shih Lin, Jong-Yuh Chang, Chih-Chiang Tu
  • Publication number: 20120207381
    Abstract: A method for inspecting a manufactured product includes applying a first test regimen to the manufactured product to identify product defects. The first test regimen produces a first set of defect candidates. The method further includes applying a second test regimen to the manufactured product to identify product defects. The second test regimen produces a second set of defect candidates, and the second test regimen is different from the first test regimen. The method also includes generating a first filtered defect set by eliminating ones of the first set of defect candidates that are not indentified in the second set of defect candidates.
    Type: Application
    Filed: February 11, 2011
    Publication date: August 16, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Biow-Hiem Ong, Chien-Hung Lai, Chih-Chiang Tu, Jong-Yuh Chang, Kuang-Yu Liu
  • Publication number: 20120051621
    Abstract: The present disclosure provides a method of inspecting a photolithographic mask wherein a design database is received, and a feature of the design database is adjusted by a bias factor to produce a biased database. Image rendering is performed on the biased database to produce a biased image. A mask is also created using the design database, and the mask is imaged to produce a mask image. The biased image is compared to the mask image, and a new value for the bias factor may be determined based on the comparison.
    Type: Application
    Filed: August 25, 2010
    Publication date: March 1, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Biow-Hiem Ong, Rick Lai, Chih-Chiang Tu, Chia-Shih Lin, Jong-Yuh Chang