Patents by Inventor Biping Wu

Biping Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8769449
    Abstract: Methods for generating a circuit design are disclosed. A plurality of cells is instantiated in the circuit design in response to user input. The set of interface parameters of each cell is arranged into a hierarchy of interface levels as indicated by an interface model corresponding to the cell. For each of the interface levels, values of the sets of interface parameters of cells included in the interface level are respectively propagated to other cells directly connected to the cell. In response to propagating a value of an interface parameter from another cell of the plurality of cells to the cell and the cell having a value of the corresponding interface parameter that is different from the propagated value, a value for the corresponding interface parameter of the cell is determined using a respective propagation function associated with the corresponding interface level.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: July 1, 2014
    Assignee: Xilinx, Inc.
    Inventors: Adam P. Donlin, Biping Wu, Kyle Corbett, Nabeel Shirazi, Shay P. Seng, Amit Kasat, Srinivas Beeravolu, Khang K. Dao, Jeffrey H. Seltzer, Christopher J. Case
  • Patent number: 8359557
    Abstract: A method is provided for generation of a circuit design. A plurality of components, including at least a processor and a peripheral device, is instantiated in a circuit design. One or more parameterizable data bus interface blocks are automatically selected based on the master-slave relationships, requirements, and capabilities of the components. The one or more parameterizable data bus interface blocks are instantiated in the circuit design. In response to user input, values are assigned to one or more parameters of the processor. The plurality of components and data bus interface blocks are automatically parameterized by determining appropriate parameter values according to the parameters of the processor and capabilities and requirements of the components and data bus interface blocks.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: January 22, 2013
    Assignee: Xilinx, Inc.
    Inventors: Xi Chen, Jibin Han, Paulo L. Dutra, Thien Than, Biping Wu