Abstract: Embodiments of the present disclosure provide an apparatus including a memory array including a plurality of sub-arrays. A plurality of temporary storage units (TSUs) is coupled to the plurality of sub-arrays. Each TSU indicates whether the respective sub-array is undergoing one of a read operation and a write operation. A control circuit is coupled to each of the plurality of sub-arrays through a data bus. The control circuit transmits a read pulse or a write pulse as a first pulse with a delay in response to the sub-array undergoing the read operation or the write operation and transmits, instantaneously, the first pulse to one of the plurality of sub-arrays in response to the sub-array not undergoing the read operation or the write operation.

Abstract: Disclosed is a memory structure with reference-free single-ended sensing. The structure includes an array of non-volatile memory (NVM) cells (e.g., resistance programmable NVM cells) and a sense circuit connected to the array via a data line and a column decoder. The sense circuit includes field effect transistors (FETs) connected in parallel between an output node and a switch and inverters connected between the data line and the gates of the FETs, respectively. To determine the logic value of a stored bit, the inverters are used to detect whether or not a voltage drop occurs on the data line within a predetermined period of time. Using redundant inverters to control redundant FETs connected to the output node increases the likelihood that the occurrence of the voltage drop will be detected and captured at the output node, even in the presence of process and/or thermal variations. Also disclosed is a sensing method.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Abstract: The present disclosure relates to a structure including a latch circuit, a first non-volatile field effect transistor (FET) connecting to a first side of the latch circuit and a bit line, and a second non-volatile field effect transistor (FET) connecting to a second side of the latch circuit and a complementary bit line.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Abstract: Embodiments of the disclosure provide a system for providing a true random number (TRN) or physically unclonable function (PUF), including: an array of voltage controlled magnetic anisotropy (VCMA) cells; a voltage pulse tuning circuit for generating and applying a stochastically tuned voltage pulse to the VCMA cells in the array of VCMA cells, wherein the stochastically tuned voltage pulse has a magnitude and duration that provides a 50%-50% switching distribution of the VCMA cells in the array of VCMA cells; and a bit output system for reading a state of each of the VCMA cells in the array of VCMA cells to provide a TRN or PUF.

Abstract: The present disclosure relates to a structure including a latch circuit, a first non-volatile field effect transistor (FET) connecting to a first side of the latch circuit and a bit line, and a second non-volatile field effect transistor (FET) connecting to a second side of the latch circuit and a complementary bit line.

Abstract: Structures and static random access memory bit cells including complementary field effect transistors and methods of forming such structures and bit cells. A first complementary field-effect transistor has a first storage nanosheet transistor, a second storage nanosheet transistor stacked over the first storage nanosheet transistor, and a first gate electrode shared by the first storage nanosheet transistor and the second storage nanosheet transistor. A second complementary field-effect transistor has a third storage nanosheet transistor, a fourth storage nanosheet transistor stacked over the third storage nanosheet transistor, and a second gate electrode shared by the third storage nanosheet transistor and the fourth storage nanosheet transistor. The first gate electrode and the second gate electrode are arranged in a spaced arrangement along a longitudinal axis. All gate electrodes of the SRAM bitcell may be arranged in a 1CPP layout.

Abstract: Disclosed are embodiments of a non-volatile static random access memory (NV-SRAM) cell. The NV-SRAM cell includes a static random access memory (SRAM) circuit (e.g., a conventional high performance, high reliability SRAM circuit). However, in order to avoid volatility while still retaining the advantages associated with SRAM circuit operation, the NV-SRAM cell also includes a pair of NVM circuits. These NVM circuits capture data values stored on the data nodes of the SRAM circuit prior to power down and rewrite those data values back onto the data nodes of the SRAM circuit upon power up. Also disclosed are embodiments of a method of operating a selected NV-SRAM cell in a memory array.

Abstract: The present disclosure relates to a structure including a plurality of magnetic random access memory (MRAM) bitcells including a first circuit and a second circuit, the second circuit being connected to a same wordline as the first circuit such that the second circuit is configured as a parallel series connection to generate a reference resistance value for sensing.

Abstract: One illustrative device includes an array of memory cells including a first row of memory cells and a second row of memory cells adjacent the first row, a first gate structure extending along the first row, a second gate structure extending along the second row, a first wordline positioned in a first layer above the array and contacting the first gate structure, and a second wordline positioned in a second layer above the first layer and contacting the second gate structure, wherein the second wordline vertically overlaps the first wordline.

Abstract: The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin.

Abstract: Disclosed is a reference circuit having an even number m of groups of m parallel-connected magnetic tunnel junctions (MTJs). The MTJs in half of the groups are programmed to have parallel resistances (RP) and the MTJs in the other half are programmed to have anti-parallel resistances (RAP). Switches connect the groups in series, creating a series-parallel resistor network. The total resistance (RT) of the network has low variability and is essentially equal to half the sum of a nominal RP plus a nominal RAP and can be employed as a reference resistance (RREF). Under specific biasing conditions the series-parallel resistor network can generate a low variability reference parameter (XREF) that is dependent on this RREF. Also disclosed are an integrated circuit (IC) that includes the reference circuit and a magnetic random access memory (MRAM) structure, which uses XREF to determine stored data values in MRAM cells and associated methods.

Abstract: The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin.

Abstract: Embodiments of the disclosure provide a system for providing a true random number (TRN) or physically unclonable function (PUF), including: an array of voltage controlled magnetic anisotropy (VCMA) cells; a voltage pulse tuning circuit for generating and applying a stochastically tuned voltage pulse to the VCMA cells in the array of VCMA cells, wherein the stochastically tuned voltage pulse has a magnitude and duration that provides a 50%-50% switching distribution of the VCMA cells in the array of VCMA cells; and a bit output system for reading a state of each of the VCMA cells in the array of VCMA cells to provide a TRN or PUF.

Abstract: The disclosure provides a circuit structure and method to provide self-aligned contacts in a zero-via conductor layer. The structure may include a device layer including a first contact to a first source/drain region, and a second contact to a second source/drain region, the first and second source/drain regions being separated by a transistor gate. A zero-via layer of the circuit structure may include: a first via conductor positioned on the first contact and self-aligned with an overlying metal level in a first direction; and a second via conductor positioned on the second contact and self-aligned with the overlying metal level in a second direction, the second direction being orthogonal to the first direction.

Abstract: Disclosed is a reference circuit having an even number m of groups of m parallel-connected magnetic tunnel junctions (MTJs). The MTJs in half of the groups are programmed to have parallel resistances (RP) and the MTJs in the other half are programmed to have anti-parallel resistances (RAP). Switches connect the groups in series, creating a series-parallel resistor network. The total resistance (RT) of the network has low variability and is essentially equal to half the sum of a nominal RP plus a nominal RAP and can be employed as a reference resistance (RREF). Under specific biasing conditions the series-parallel resistor network can generate a low variability reference parameter (XREF) that is dependent on this RREF. Also disclosed are an integrated circuit (IC) that includes the reference circuit and a magnetic random access memory (MRAM) structure, which uses XREF to determine stored data values in MRAM cells and associated methods.

Abstract: The disclosure provides a circuit structure and method to provide self-aligned contacts in a zero-via conductor layer. The structure may include a device layer including a first contact to a first source/drain region, and a second contact to a second source/drain region, the first and second source/drain regions being separated by a transistor gate. A zero-via layer of the circuit structure may include: a first via conductor positioned on the first contact and self-aligned with an overlying metal level in a first direction; and a second via conductor positioned on the second contact and self-aligned with the overlying metal level in a second direction, the second direction being orthogonal to the first direction.

Abstract: The disclosure provides a circuit structure for storage and retrieval of data, and related methods. The circuit structure may include drive transistor having a source terminal, a drain terminal, and a gate terminal coupled to a word line. A first resistive memory element coupled between the source terminal of the drive transistor and a first bit line may be in a first memory state. A second resistive memory element coupled between the drain terminal of the drive transistor and a second bit line may be in a second memory state opposite the first memory state. The structure may also include a read transistor having a source terminal coupled to the drain terminal of the drive transistor, a drain terminal coupled to ground, and a gate terminal coupled to a select line.

Abstract: The disclosure provides a circuit structure for storage and retrieval of data, and related methods. The circuit structure may include drive transistor having a source terminal, a drain terminal, and a gate terminal coupled to a word line. A first resistive memory element coupled between the source terminal of the drive transistor and a first bit line may be in a first memory state. A second resistive memory element coupled between the drain terminal of the drive transistor and a second bit line may be in a second memory state opposite the first memory state. The structure may also include a read transistor having a source terminal coupled to the drain terminal of the drive transistor, a drain terminal coupled to ground, and a gate terminal coupled to a select line.