Patents by Inventor Birama Goumballa

Birama Goumballa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160233846
    Abstract: A calibration circuit and a method for calibrating a RC circuit, such as a high-pass filter, of an integrated circuit are provided. The calibration circuit comprises a filter arrangement having tuneable filter for filtering an input signal having a predetermined frequency. The filter comprises tuneable resistor elements, a saturation detector for detecting saturation and non-saturation of the tuneable filter by comparing a comparison voltage with the signal voltage of the filtered input signal, calibration control logic for providing incrementing and decrementing counter signals.
    Type: Application
    Filed: September 27, 2013
    Publication date: August 11, 2016
    Inventors: Cristian PAVAO-MOREIRA, Olivier DOARE, Birama GOUMBALLA
  • Patent number: 9407199
    Abstract: An integrated circuit comprises a frequency dependent circuit comprising an input node, an output node and a main bank of selectable first capacitive elements that affect a frequency characteristic of the frequency dependent circuit. The frequency dependent circuit further comprises at least one shunt bank of selectable second capacitive elements located between ground and one of the input node or the output node, wherein at least one selectable second capacitive element switched out of the frequency dependent circuit is based on a number of the selectable first capacitive elements that are switched into the frequency dependent circuit.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: August 2, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cristian Pavao-Moreira, Birama Goumballa, Yi Yin
  • Patent number: 9401723
    Abstract: An XOR phase detector for a phase-locked loop PLL comprises an XOR gate which has an input for a periodic reference signal and another input connected to a frequency divider of the PLL. A level shifter has a level shifter input connected to an output of the XOR gate and a level shifter output connectable to a voltage-controlled oscillator VCO of the PLL. The level shifter is connectable between low and high voltage providers and has a high level and a low level. The level shifter is arranged to deliver at its output the high level or the low level depending on whether the voltage at the output of the XOR phase detector is low or high. The level shifter further has a setpoint input for setting the high level to a setpoint level.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: July 26, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gilles Montoriol, Olivier Vincent Doare, Birama Goumballa, Didier Salle
  • Patent number: 9395740
    Abstract: A temperature coefficient factor circuit is provided which generates a current which varies with temperature according to a programmable temperature coefficient factor. The temperature coefficient factor circuit comprises a first current source providing a first current with a positive temperature coefficient factor, a second current source providing a second current with a negative temperature coefficient factor, a common terminal, a first programmable amplifying current mirror, a second programmable amplifying current mirror and a current output circuit. The first programmable amplifying current mirror provides in dependence of a control signal ctrl an amplified first current to the common terminal. The second programmable amplifying current mirror conducts away in dependence of the control signal ctrl an amplified second current from the common terminal. The current output circuit provides the output current based on a difference current between the amplified first current and the amplified second current.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: July 19, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cristian Pavao-Moreira, Birama Goumballa, Didier Salle
  • Publication number: 20160182064
    Abstract: A charge pump circuit comprises a first bipolar transistor device and a second bipolar switching device arranged in a differential pair configuration. A first terminal of each of the first and second bipolar switching devices are coupled to a supply. A second like terminal of each of the first and second bipolar switching devices are coupled together and to ground potential via a pulsed current source. A field effect switching device is also provided and the first terminal of the first bipolar switching device is coupled to the voltage supply via the field effect switching device.
    Type: Application
    Filed: July 18, 2013
    Publication date: June 23, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Birama GOUMBALLA, Gilles Montoriol, Didier SALLE
  • Publication number: 20160173109
    Abstract: An XOR phase detector for a phase-locked loop PLL comprises an XOR gate which has an input for a periodic reference signal and another input connected to a frequency divider of the PLL. A level shifter has a level shifter input connected to an output of the XOR gate and a level shifter output connectable to a voltage-controlled oscillator VCO of the PLL. The level shifter is connectable between low and high voltage providers and has a high level and a low level. The level shifter is arranged to deliver at its output the high level or the low level depending on whether the voltage at the output of the XOR phase detector is low or high. The level shifter further has a setpoint input for setting the high level to a setpoint level.
    Type: Application
    Filed: May 12, 2015
    Publication date: June 16, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: GILLES MONTORIOL, OLIVIER VINCENT DOARE, BIRAMA GOUMBALLA, DIDIER SALLE
  • Publication number: 20160154092
    Abstract: An integrated circuit for saturation detection comprises: a plurality of gain components; a plurality of saturation detectors with each saturation detector operably coupled to an output of one of the gain components; a plurality of logic elements with a first input of each logic element associated with an output of one of the saturation detectors; and a controller operably coupled to the plurality of logic elements. The controller is arranged to apply a signal to a second input of individual ones of the plurality of logic elements such that an output of the respective logic element identifies a saturation event of the saturation detector associated with that respective logic element.
    Type: Application
    Filed: May 4, 2015
    Publication date: June 2, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: CRISTIAN PAVAO-MOREIRA, DOMINIQUE DELBECQ, BIRAMA GOUMBALLA, DIDIER SALLE
  • Publication number: 20160103206
    Abstract: A radar device comprises at least one transmitter unit for transmitting a radar signal, at least one receiver unit for receiving a reflected radar signal, and a phase shift unit for producing a phase shift in the frequency modulated radar signal in response to a phase shift signal. The receiver unit comprises at least one filter unit for filtering the received signal and is arranged for resetting the filter unit in response to said phase shift signal, so as to avoid saturation of the filter unit due to the phase shift.
    Type: Application
    Filed: March 9, 2015
    Publication date: April 14, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: CRISTIAN PAVAO-MOREIRA, DOMINIQUE DELBECQ, BIRAMA GOUMBALLA
  • Publication number: 20160065131
    Abstract: An integrated circuit comprises a frequency dependent circuit comprising an input node, an output node and a main bank of selectable first capacitive elements that affect a frequency characteristic of the frequency dependent circuit. The frequency dependent circuit further comprises at least one shunt bank of selectable second capacitive elements located between ground and one of the input node or the output node, wherein at least one selectable second capacitive element switched out of the frequency dependent circuit is based on a number of the selectable first capacitive elements that are switched into the frequency dependent circuit.
    Type: Application
    Filed: January 27, 2015
    Publication date: March 3, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: CRISTIAN PAVAO-MOREIRA, BIRAMA GOUMBALLA, YI YIN
  • Publication number: 20160065225
    Abstract: A method of re-centering a voltage controlled oscillator of a wireless device comprising a phase locked loop circuit is described. The method comprises receiving an input frequency signal at a phase detector of the phase locked loop circuit from a frequency source; generating an oscillator signal based on the received frequency signal; selectably opening a feedback loop of the phase locked loop circuit when in a calibration mode of operation, performing coarse frequency tuning of the oscillator output signal; performing fine frequency tuning of a coarsely adjusted oscillator output signal; and closing the feedback loop.
    Type: Application
    Filed: January 27, 2015
    Publication date: March 3, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: CRISTIAN PAVAO-MOREIRA, BIRAMA GOUMBALLA, YI YIN
  • Publication number: 20150349729
    Abstract: The present invention relates to an amplifier circuit, comprising: first to fourth semiconductor amplifiers for controlling first to fourth currents between supply and output terminals, a first input terminal connected to provide a first input signal to a first control terminal of the first semiconductor amplifier and to a fourth control terminal of the fourth semiconductor amplifier, and a second input terminal connected to provide a second input signal to a second control terminal of the second semiconductor amplifier and to a third control terminal of the third semiconductor amplifier. The present invention also relates to a bi-stage amplifier circuit, and to a multi-stage amplifier circuit comprising a cascade of a number of amplifier circuits complying to the present invention, the multi-stage amplifier circuit having a gain control logic prepared to control a gain of at least one of the amplifier circuits.
    Type: Application
    Filed: December 1, 2014
    Publication date: December 3, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: CRISTIAN PAVAO-MOREIRA, BIRAMA GOUMBALLA
  • Publication number: 20150309527
    Abstract: A temperature coefficient factor circuit is provided which generates a current which varies with temperature according to a programmable temperature coefficient factor. The temperature coefficient factor circuit comprises a first current source providing a first current with a positive temperature coefficient factor, a second current source providing a second current with a negative temperature coefficient factor, a common terminal, a first programmable amplifying current mirror, a second programmable amplifying current mirror and a current output circuit. The first programmable amplifying current mirror provides in dependence of a control signal ctrl an amplified first current to the common terminal. The second programmable amplifying current mirror conducts away in dependence of the control signal ctrl an amplified second current from the common terminal. The current output circuit provides the output current based on a difference current between the amplified first current and the amplified second current.
    Type: Application
    Filed: November 7, 2012
    Publication date: October 29, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Cristian PAVAO-MOREIRA, Birama GOUMBALLA, Didier SALLE
  • Patent number: 9094032
    Abstract: An integrated circuit device comprises at least one digital to analogue converter module. The DAC module includes at least one current replicator component having a first channel terminal, a second channel terminal and a reference voltage terminal arranged to receive a reference voltage signal; the at least one current replicator component being arranged to moderate a current flowing between the first and second channel terminals based at least partly on the received reference voltage signal. The DAC module also includes at least one filter component coupled to the reference voltage terminal to perform filtering of the reference voltage signal.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: July 28, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Stephane Dugalleix, Birama Goumballa, Gilles Montoriol
  • Publication number: 20140152481
    Abstract: An integrated circuit device comprises at least one digital to analogue converter module. The DAC module includes at least one current replicator component having a first channel terminal, a second channel terminal and a reference voltage terminal arranged to receive a reference voltage signal; the at least one current replicator component being arranged to moderate a current flowing between the first and second channel terminals based at least partly on the received reference voltage signal. The DAC module also includes at least one filter component coupled to the reference voltage terminal to perform filtering of the reference voltage signal.
    Type: Application
    Filed: July 20, 2011
    Publication date: June 5, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Stephane Dugalleix, Birama Goumballa, Gilles Montoriol