Patents by Inventor Biranchinath Sahu
Biranchinath Sahu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11742754Abstract: A one-shot inductor current scheme which includes a controller to generate a signal to control a high-side switch and a low-side switch such that the high-side switch remains turned on beyond a turn-on time if a voltage level on an output supply rail remains below a reference. The scheme reduces the minimum operating voltage Vmin and/or frequency guard-band of the SoCs (system-on-chips).Type: GrantFiled: October 13, 2020Date of Patent: August 29, 2023Assignee: Intel CorporationInventors: Anup J Deka, Shobhit Tyagi, Sudhir Polarouthu, Biranchinath Sahu
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Publication number: 20210124382Abstract: A one-shot inductor current scheme which includes a controller to generate a signal to control a high-side switch and a low-side switch such that the high-side switch remains turned on beyond a turn-on time if a voltage level on an output supply rail remains below a reference. The scheme reduces the minimum operating voltage Vmin and/or frequency guard-band of the SoCs (system-on-chips).Type: ApplicationFiled: October 13, 2020Publication date: April 29, 2021Applicant: Intel CorporationInventors: Anup J. Deka, Shobhit Tyagi, Sudhir Polarouthu, Biranchinath Sahu
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Patent number: 10084307Abstract: The disclosure provides an over-current protection circuit. A signal generating block in the over-current protection circuit generates one or more input voltages, a summed voltage and an average voltage in response to one or more differential voltages. A control block generates one or more control signals in response to the one or more input voltages and the average voltage. An analog control loop block generates an initiation signal in response to the summed voltage and an output voltage. A phase control logic block generates one or more PWM (pulse width modulated) signals in response to the initiation signal and the one or more control signals.Type: GrantFiled: April 28, 2016Date of Patent: September 25, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Pradeep V S R Pydah, Biranchinath Sahu, Tetsuo Tateishi, Kuang-Yao Cheng, Nandakishore Raimar
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Patent number: 9817414Abstract: Undershoot reduction circuitry includes, for example, a first comparator, a second comparator, and a controller. The first comparator is operable for comparing an indication of a power supply voltage output against a first threshold. The second comparator is operable for comparing an indication of the power supply voltage output against a second threshold. The controller is operable for generating a first power control signal to raise the power supply voltage output when the indication of the power supply voltage output has a first slope and crosses the first threshold and to lower the power supply voltage output when the indication of the power supply voltage output has an opposite slope and crosses the second threshold.Type: GrantFiled: April 13, 2015Date of Patent: November 14, 2017Assignee: Texas Instruments IncorporatedInventors: Naga Venkata Prasadu Mangina, Biranchinath Sahu, Pradeep V S R Pydah, Nandakishore Raimar
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Publication number: 20170317488Abstract: The disclosure provides an over-current protection circuit. A signal generating block in the over-current protection circuit generates one or more input voltages, a summed voltage and an average voltage in response to one or more differential voltages. A control block generates one or more control signals in response to the one or more input voltages and the average voltage. An analog control loop block generates an initiation signal in response to the summed voltage and an output voltage. A phase control logic block generates one or more PWM (pulse width modulated) signals in response to the initiation signal and the one or more control signals.Type: ApplicationFiled: April 28, 2016Publication date: November 2, 2017Inventors: Pradeep V S R PYDAH, Biranchinath SAHU, Tetsuo TATEISHI, Kuang-Yao CHENG, Nandakishore RAIMAR
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Publication number: 20160299520Abstract: Undershoot reduction circuitry includes, for example, a first comparator, a second comparator, and a controller. The first comparator is operable for comparing an indication of a power supply voltage output against a first threshold. The second comparator is operable for comparing an indication of the power supply voltage output against a second threshold. The controller is operable for generating a first power control signal to raise the power supply voltage output when the indication of the power supply voltage output has a first slope and crosses the first threshold and to lower the power supply voltage output when the indication of the power supply voltage output has an opposite slope and crosses the second threshold.Type: ApplicationFiled: April 13, 2015Publication date: October 13, 2016Inventors: Prasadu Mangina, Biranchinath Sahu, Pradeep Pydah, Nandakishore Raimar
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Patent number: 9397564Abstract: A switching regulator comprising a droop amplifier responsive to a reference voltage and a feedback voltage to generate a droop voltage. The droop amplifier includes a boost circuit configurable to increase a transconductance of the droop amplifier during an upward transition of the reference voltage. The switching regulator further includes a comparator responsive to the droop voltage and a current sense signal. The comparator is configured to initiate switching in the switching regulator.Type: GrantFiled: September 27, 2012Date of Patent: July 19, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Biranchinath Sahu, Jitendra K. Agrawal, Dattatreya B. S.
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Publication number: 20140084887Abstract: A switching regulator comprising a droop amplifier responsive to a reference voltage and a feedback voltage to generate a droop voltage. The droop amplifier includes a boost circuit configurable to increase a transconductance of the droop amplifier during an upward transition of the reference voltage. The switching regulator further includes a comparator responsive to the droop voltage and a current sense signal. The comparator is configured to initiate switching in the switching regulator.Type: ApplicationFiled: September 27, 2012Publication date: March 27, 2014Applicant: Texas Instruments IncorporatedInventors: Biranchinath Sahu, Jitendra K. Agrawal, Dattatreya B.S.
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Patent number: 8638080Abstract: Circuits and methods for controlling Pulse Width Modulation (PWM) input of a driver circuit during transition of states are provided. The driver circuit is operative in one of a high state, a low state and a tri-state based on the PWM input. The method includes receiving a tri-state command for transition from the high state to the tri-state. A PWM output signal is enabled to transition from a high logic value to a low logic value for driving the driver circuit from the high state to the low state upon receipt of the tri-state command. The PWM output signal is enabled to transition from the low logic value to a tri-state logic value for driving the driver circuit from the low state to the tri-state upon elapse of a threshold time delay. The PWM input to the driver circuit is based on the PWM output signal.Type: GrantFiled: September 14, 2011Date of Patent: January 28, 2014Assignee: Texas Instruments IncorporatedInventors: Jitendra Kumar Agrawal, Biranchinath Sahu
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Publication number: 20130063114Abstract: Circuits and methods for controlling Pulse Width Modulation (PWM) input of a driver circuit during transition of states are provided. The driver circuit is operative in one of a high state, a low state and a tri-state based on the PWM input. The method includes receiving a tri-state command for transition from the high state to the tri-state. A PWM output signal is enabled to transition from a high logic value to a low logic value for driving the driver circuit from the high state to the low state upon receipt of the tri-state command. The PWM output signal is enabled to transition from the low logic value to a tri-state logic value for driving the driver circuit from the low state to the tri-state upon elapse of a threshold time delay. The PWM input to the driver circuit is based on the PWM output signal.Type: ApplicationFiled: September 14, 2011Publication date: March 14, 2013Applicant: Texas Instruments IncorporatedInventors: Jitendra Kumar Agrawal, Biranchinath Sahu
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Patent number: 8041975Abstract: The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.Type: GrantFiled: May 13, 2008Date of Patent: October 18, 2011Assignee: Silicon Laboratories Inc.Inventors: Biranchinath Sahu, Douglas F. Pastorello, Golam R. Chowdhury
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Patent number: 8010819Abstract: A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.Type: GrantFiled: October 21, 2008Date of Patent: August 30, 2011Assignee: Silicon LaboratoriesInventors: Douglas F. Pastorello, Douglas Holberg, William Gene Durbin, Biranchinath Sahu, Golam R. Chowdhury
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Patent number: 7903433Abstract: A converter for a multi-phase current network can include a plurality of current sensors, each of the plurality of current sensors being configured to detect current for a respective phase of the multi-phase network. A current averaging circuit is configured to provide an indication of the average current for the multi-phase network based on the current detected by each of the plurality of current sensors. A modulator is configured to modulate at least one phase of the multi-phase network independently of each other phase of the multi-phase network based on a difference between the current detected for the at least one phase and the average current for the multi-phase network.Type: GrantFiled: December 26, 2007Date of Patent: March 8, 2011Assignee: Texas Instruments IncorporatedInventors: Brian A. Carpenter, Christopher J. Sanzo, Biranchinath Sahu, Tetsuo Tateishi
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Patent number: 7888923Abstract: An apparatus is provided. The apparatus comprises a current sensor, an error amplifier, a comparator, an analog-to-digital converter (ADC), control logic, and drivers. The error amplifier is adapted to receive a reference voltage and a feedback voltage, and the comparator has a first input terminal and a second input terminal, where the sum of at least a first portion of a common mode voltage and an output of the error amplifier is input into the first input terminal, and wherein the sum of at least a second portion of the common mode voltage and an output of the current sensor is input into the second input terminal. The ADC receives the sum of the second portion of the common mode voltage and the output of the current senor. Additionally, the ADC has a plurality of internal threshold voltages that are between the common mode voltage and an overcurrent limit adjustment voltage.Type: GrantFiled: March 27, 2009Date of Patent: February 15, 2011Assignee: Texas Instruments IncorporatedInventor: Biranchinath Sahu
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Patent number: 7855905Abstract: A digital power supply controller is disclosed for controlling the operation of a switched power supply. The controller is contained within an integrated circuit package enclosing an integrated circuit chip. A plurality of inputs are provided on the package for interfacing with the switched power supply for receiving sensed inputs therefrom. A plurality of outputs provide switch control signals for turning on and off switches in the switched power supply. An integrated digital controller on the chip receives the inputs and generates the outputs, and includes an integrated instruction based processing engine for providing a portion of the digital control of the digital controller. A memory associated with the processing engine stores instructions for the processing engine.Type: GrantFiled: September 16, 2008Date of Patent: December 21, 2010Assignee: Silicon Laboratories Inc.Inventors: Ka Y. Leung, Kafai Leung, Jinwen Xaio, Chia-Ling Wei, Alvin C. Storvik, II, Biranchinath Sahu, Donald Alfano
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Publication number: 20100246221Abstract: An apparatus is provided. The apparatus comprises a current sensor, an error amplifier, a comparator, an analog-to-digital converter (ADC), control logic, and drivers. The error amplifier is adapted to receive a reference voltage and a feedback voltage, and the comparator has a first input terminal and a second input terminal, where the sum of at least a first portion of a common mode voltage and an output of the error amplifier is input into the first input terminal, and wherein the sum of at least a second portion of the common mode voltage and an output of the current sensor is input into the second input terminal. The ADC receives the sum of the second portion of the common mode voltage and the output of the current senor. Additionally, the ADC has a plurality of internal threshold voltages that are between the common mode voltage and an overcurrent limit adjustment voltage.Type: ApplicationFiled: March 27, 2009Publication date: September 30, 2010Applicant: Texas Instruments IncorporatedInventor: Biranchinath Sahu
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Patent number: 7773011Abstract: One embodiment of the invention includes a digital-to-analog converter (DAC) circuit. The DAC circuit includes a DAC portion configured to generate an output voltage having a magnitude that varies based on a plurality of digital values of a digital input signal. The DAC circuit also includes a test portion configured to compare the output voltage with a predetermined test voltage for each of the plurality of digital values of the digital input signal during a test mode. The test portion can provide a digital output signal corresponding to one of acceptance and failure of the DAC circuit.Type: GrantFiled: August 8, 2008Date of Patent: August 10, 2010Assignee: Texas Instruments IncorporatedInventors: Biranchinath Sahu, Christopher Sanzo
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Patent number: 7728749Abstract: Various apparatuses, methods and systems for a multi-mode DAC with selectable output range, granularity and offset and controlled slew rate are disclosed herein. For example, some embodiments of the present invention provide an apparatus for supplying a reference signal, including a digital-to-analog converter, a counter and a clock. The digital-to-analog converter has a digital input and an analog output that supplies a reference signal based on the digital input. The counter has a digital control word input, a clock input, a clock enable output and a count output connected to the digital input of the digital-to-analog converter. The counter is adapted to assert the clock enable output when the digital control word input requests an output count that is different from an actual count at the count output of the counter. The clock has an enable input connected to the clock enable output of the counter and a clock output connected to the clock input of the counter.Type: GrantFiled: August 22, 2008Date of Patent: June 1, 2010Assignee: Texas Instruments IncorporatedInventor: Biranchinath Sahu
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Publication number: 20100033358Abstract: One embodiment of the invention includes a digital-to-analog converter (DAC) circuit. The DAC circuit includes a DAC portion configured to generate an output voltage having a magnitude that varies based on a plurality of digital values of a digital input signal. The DAC circuit also includes a test portion configured to compare the output voltage with a predetermined test voltage for each of the plurality of digital values of the digital input signal during a test mode. The test portion can provide a digital output signal corresponding to one of acceptance and failure of the DAC circuit.Type: ApplicationFiled: August 8, 2008Publication date: February 11, 2010Inventors: Biranchinath Sahu, Christopher Sanzo
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Publication number: 20090187773Abstract: A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.Type: ApplicationFiled: October 21, 2008Publication date: July 23, 2009Applicant: SILICON LABORATORIES INC.Inventors: DOUGLAS F. PASTORELLO, DOUGLAS HOLBERG, WILLIAM GENE DURBIN, BIRANCHINATH SAHU, GOLAM R. CHOWDHURY