Patents by Inventor Biren Shah

Biren Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11868677
    Abstract: A remote test infrastructure can enable a developer to use a local browser to run and test an application on a remote device. The remote device is coupled to a host machine and connected via a communication network to the browser. The infrastructure can stream a video feed of the display of the remote device to the browser, enabling the developer to examine the result of testing and development of the application running on the remote device. For applications that have features requiring audio input, the infrastructure can pair an external component, such as the host machine, as a virtual audio input device, mimicking an external microphone. The virtual audio input device can capture an audio file or an audio stream and provide the audio as input to the application running on the remote device thereby simulating the application receiving an input from an external microphone.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: January 9, 2024
    Assignee: BrowserStack Limited
    Inventor: Harshit Biren Shah
  • Patent number: 8397205
    Abstract: A system and method for specifying timing relationships among nodes in a graphical program. User input specifying desired timing of a first node with respect to timing of a second node may be received. In various embodiments, any kind of timing relationship or timing constraint between the first node and the second node may be specified. Timing information may be displayed on the display to visually indicate the timing of the first node with respect to timing of the second node. In one embodiment, displaying the timing information may comprise displaying a timing wire between the first node and the second node. The graphical program may be executed in such a way that the visually indicated timing of the first node with respect to timing of the second node is satisfied.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: March 12, 2013
    Assignee: National Instruments Corporation
    Inventors: Jacob Kornerup, Jeffrey L. Kodosky, Hugo A. Andrade, Biren Shah, Aljosa Vrancic, Michael L. Santori
  • Patent number: 8359567
    Abstract: A system and method for specifying timing relationships among nodes in a graphical program. User input specifying desired timing of a first node with respect to timing of a second node may be received. In various embodiments, any kind of timing relationship or timing constraint between the first node and the second node may be specified. Timing information may be displayed on the display to visually indicate the timing of the first node with respect to timing of the second node. In one embodiment, displaying the timing information may comprise displaying a timing wire between the first node and the second node. The graphical program may be executed in such a way that the visually indicated timing of the first node with respect to timing of the second node is satisfied.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: January 22, 2013
    Assignee: National Instruments Corporation
    Inventors: Jacob Kornerup, Jeffrey L. Kodosky, Hugo A. Andrade, Biren Shah, Aljosa Vrancic, Michael L. Santori
  • Patent number: 7802229
    Abstract: A “timed loop with frames” node may be included in a graphical program. The “timed loop with frames” node may combine a timed loop with a timed sequence such that the timed sequence is executed at each iteration of the timed loop. The “timed loop with frames” node may be configured with first execution timing information that controls execution timing for the iterations of the loop. A plurality of graphical code portions may be included in the “timed loop with frames” such that a sequential order of execution for the graphical code portions is specified. The “timed loop with frames” node may be configured with second execution timing information that controls execution timing for the graphical code portions executed at each iteration.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: September 21, 2010
    Assignee: National Instruments Corporation
    Inventors: Jacob Kornerup, Biren Shah, Aljosa Vrancic, Matthew Curtis, Steve Rogers
  • Patent number: 7761847
    Abstract: A system and method for executing a plurality of graphical code portions as a timed sequence is described. The graphical code portions may be included in a graphical program and configured with information specifying a sequential order of execution and execution timing information. During execution of the graphical program, the graphical code portions are executed sequentially in the sequential order and in accordance with the execution timing information. In one embodiment a timed sequence structure node may be utilized to specify the timed sequence. For example, the user may include the timed sequence structure node in the graphical program and associate the plurality of graphical code portions with the timed sequence structure node such that the timed sequence structure node species a sequential order of execution for the graphical code portions. The user may also configure the timed sequence structure node with execution timing information for one or more of the graphical code portions.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: July 20, 2010
    Assignee: National Instruments Corporation
    Inventors: Jacob Kornerup, Biren Shah, Aljosa Vrancic
  • Patent number: 7725874
    Abstract: A combination structure node is provided by a graphical programming development environment for use in a graphical program, where the combination structure node is operable to perform two or more control flow functions. For example, the combination structure node may be operable to perform two or more of: iteration, looping, conditional branching, sequencing, timed execution, event-driven execution, or other control flow functions. A user may include the combination structure node in a graphical program and associate a graphical code portion with the combination structure node. During execution of the graphical program, the combination structure node is operable to cause the associated graphical code portion to execute according to the two or more control flow functions performed by the combination structure node.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: May 25, 2010
    Assignee: National Instruments Corporation
    Inventors: Jacob Kornerup, Biren Shah, Aljosa Vrancic, Matthew Curtis, Steve Rogers
  • Patent number: 7703034
    Abstract: A system and method for viewing timing of one or more loops in a graphical program. A graphical program having one or more loops may be created. In one embodiment the one or more loops may include one or more timed loops, i.e., the loops may be configured to execute according to particular execution periods. The graphical program may be executed, and timing analysis data regarding timing of the one or more loops during execution of the graphical program may be stored. A graphical user interface (GUI) for viewing timing of the one or more loops during execution of the graphical program may be displayed. In various embodiments the GUI may display any of various kinds of information regarding timing of the one or more loops, and any kind of visual presentation may be used in displaying the information.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: April 20, 2010
    Assignee: National Instruments Corporation
    Inventors: Jacob Kornerup, Biren Shah, Aljosa Vrancic, Bob Preis
  • Patent number: 7574690
    Abstract: A system and method for creating a graphical program operable to execute a timed loop. A loop may be displayed in the graphical program and configured with timing information in response to user input. The timing information may include an execution period which specifies a desired period at which the loop should execute during execution of the graphical program. The timing information may also include information such as a timing source, offset, and priority. During execution of the graphical program, the execution period of the loop may control the rate at which the loop executes.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: August 11, 2009
    Assignee: National Instruments Corporation
    Inventors: Biren Shah, Jacob Kornerup, Aljosa Vrancic, Jeffrey L. Kodosky, Michael L. Santori
  • Publication number: 20070203683
    Abstract: A system and method for specifying timing relationships among nodes in a graphical program. User input specifying desired timing of a first node with respect to timing of a second node may be received. In various embodiments, any kind of timing relationship or timing constraint between the first node and the second node may be specified. Timing information may be displayed on the display to visually indicate the timing of the first node with respect to timing of the second node. In one embodiment, displaying the timing information may comprise displaying a timing wire between the first node and the second node. The graphical program may be executed in such a way that the visually indicated timing of the first node with respect to timing of the second node is satisfied.
    Type: Application
    Filed: April 30, 2007
    Publication date: August 30, 2007
    Inventors: Jacob Kornerup, Jeffrey Kodosky, Hugo Andrade, Biren Shah, Aljosa Vrancic, Michael Santori
  • Patent number: 7120874
    Abstract: System and method for filtering attributes of a graphical program element (GPE) in a graphical program or diagram, e.g., a property node, menu, property page, icon palette, etc., based on targeted or configured resources. Input is received specifying or selecting a filter option from presented filter options. The filter options include 1) display all attributes of the GPE; 2) display attributes of the GPE associated with configured resources; and 3) display attributes of the GPE associated with selected configured resources. User input is received to access the GPE. Attributes for the GPE associated with the resources are retrieved from the database and displayed in accordance with the selected filtering option. The filtered attributes of the element are then selectable by a user for various operations, e.g., to configure the graphical program, to configure resources, to initiate a purchase or order for the resources, and/or to install the resources, among others.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: October 10, 2006
    Assignee: National Instruments Corporation
    Inventors: Biren Shah, Stephen Thorne, Matthew Novacek
  • Publication number: 20060053408
    Abstract: A combination structure node is provided by a graphical programming development environment for use in a graphical program, where the combination structure node is operable to perform two or more control flow functions. For example, the combination structure node may be operable to perform two or more of: iteration, looping, conditional branching, sequencing, timed execution, event-driven execution, or other control flow functions. A user may include the combination structure node in a graphical program and associate a graphical code portion with the combination structure node. During execution of the graphical program, the combination structure node is operable to cause the associated graphical code portion to execute according to the two or more control flow functions performed by the combination structure node.
    Type: Application
    Filed: August 15, 2005
    Publication date: March 9, 2006
    Inventors: Jacob Kornerup, Biren Shah, Aljosa Vrancic, Matthew Curtis, Steve Rogers
  • Publication number: 20060053409
    Abstract: A “timed loop with frames” node may be included in a graphical program. The “timed loop with frames” node may combine a timed loop with a timed sequence such that the timed sequence is executed at each iteration of the timed loop. The “timed loop with frames” node may be configured with first execution timing information that controls execution timing for the iterations of the loop. A plurality of graphical code portions may be included in the “timed loop with frames” such that a sequential order of execution for the graphical code portions is specified. The “timed loop with frames” node may be configured with second execution timing information that controls execution timing for the graphical code portions executed at each iteration.
    Type: Application
    Filed: August 15, 2005
    Publication date: March 9, 2006
    Inventors: Jacob Kornerup, Biren Shah, Aljosa Vrancic, Matthew Curtis, Steve Rogers
  • Publication number: 20060026560
    Abstract: A system and method for executing a plurality of graphical code portions as a timed sequence is described. The graphical code portions may be included in a graphical program and configured with information specifying a sequential order of execution and execution timing information. During execution of the graphical program, the graphical code portions are executed sequentially in the sequential order and in accordance with the execution timing information. In one embodiment a timed sequence structure node may be utilized to specify the timed sequence. For example, the user may include the timed sequence structure node in the graphical program and associate the plurality of graphical code portions with the timed sequence structure node such that the timed sequence structure node species a sequential order of execution for the graphical code portions. The user may also configure the timed sequence structure node with execution timing information for one or more of the graphical code portions.
    Type: Application
    Filed: August 15, 2005
    Publication date: February 2, 2006
    Inventors: Jacob Kornerup, Biren Shah, Aljosa Vrancic
  • Publication number: 20050055666
    Abstract: A system and method for specifying timing relationships among nodes in a graphical program. User input specifying desired timing of a first node with respect to timing of a second node may be received. In various embodiments, any kind of timing relationship or timing constraint between the first node and the second node may be specified. Timing information may be displayed on the display to visually indicate the timing of the first node with respect to timing of the second node. In one embodiment, displaying the timing information may comprise displaying a timing wire between the first node and the second node. The graphical program may be executed in such a way that the visually indicated timing of the first node with respect to timing of the second node is satisfied.
    Type: Application
    Filed: July 16, 2004
    Publication date: March 10, 2005
    Inventors: Jacob Kornerup, Jeffrey Kodosky, Hugo Andrade, Biren Shah, Aljosa Vrancic, Michael Santori
  • Publication number: 20050050515
    Abstract: A system and method for creating a graphical program operable to execute a timed loop. A loop may be displayed in the graphical program and configured with timing information in response to user input. The timing information may include an execution period which specifies a desired period at which the loop should execute during execution of the graphical program. The timing information may also include information such as a timing source, offset, and priority. During execution of the graphical program, the execution period of the loop may control the rate at which the loop executes.
    Type: Application
    Filed: July 16, 2004
    Publication date: March 3, 2005
    Inventors: Biren Shah, Jacob Kornerup, Aljosa Vrancic, Jeffrey Kodosky, Michael Santori
  • Publication number: 20050034106
    Abstract: A system and method for viewing timing of one or more loops in a graphical program. A graphical program having one or more loops may be created. In one embodiment the one or more loops may include one or more timed loops, i.e., the loops may be configured to execute according to particular execution periods. The graphical program may be executed, and timing analysis data regarding timing of the one or more loops during execution of the graphical program may be stored. A graphical user interface (GUI) for viewing timing of the one or more loops during execution of the graphical program may be displayed. In various embodiments the GUI may display any of various kinds of information regarding timing of the one or more loops, and any kind of visual presentation may be used in displaying the information.
    Type: Application
    Filed: July 16, 2004
    Publication date: February 10, 2005
    Inventors: Jacob Kornerup, Biren Shah, Aljosa Vrancic, Bob Preis
  • Publication number: 20030231211
    Abstract: System and method for filtering attributes of a graphical program element (GPE) in a graphical program or diagram, e.g., a property node, menu, property page, icon palette, etc., based on targeted or configured resources. Input is received specifying or selecting a filter option from presented filter options. The filter options include 1) display all attributes of the GPE; 2) display attributes of the GPE associated with configured resources; and 3) display attributes of the GPE associated with selected configured resources. User input is received to access the GPE. Attributes for the GPE associated with the resources are retrieved from the database and displayed in accordance with the selected filtering option. The filtered attributes of the element are then selectable by a user for various operations, e.g., to configure the graphical program, to configure resources, to initiate a purchase or order for the resources, and/or to install the resources, among others.
    Type: Application
    Filed: June 18, 2002
    Publication date: December 18, 2003
    Inventors: Biren Shah, Stephen Thorne, Matthew Novacek
  • Patent number: 6310910
    Abstract: A modem includes a high speed parallel processing transmitter, receiver and decoder. Each of the transmitting and receiving portions of the modem include a plurality of parallel processing channels that process data in a sub-band. Each of the processing channels can operate at a rate which is less than the overall rate at which data is processed. In each channel is a unique word sub-band filter and a data sub-band filter that are selectively enabled to filter data in the channel. The unique word filters in the transmitting portion of the modem are specifically tuned to make the unique word that precedes the data portion of a data burst easy to detect. In the receiving portion of the modem, the unique word sub-band filters are tuned to quickly detect the unique word. Once a unique word has been received, the data sub-band filters in the receiving portion of the modem are enabled in each of the channels to filter the data portion of a burst.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: October 30, 2001
    Assignee: Teledesic LLC
    Inventors: Biren Shah, Sami Hinedi