Patents by Inventor Birendra Agarwala
Birendra Agarwala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8466056Abstract: A metal interconnect structure in ultra low-k dielectrics is described having a capped interconnect layer; an interconnect feature with a contact via and a contact line formed in a dielectric layer, where the via is partially embedded into the interconnect layer; and a thin film formed on the dielectric layer and separating the dielectric layer from the contact line. A method of fabricating the interconnect structure is also described and includes forming a first dielectric on a capped interconnect element; forming a thin film over the first dielectric; forming a second dielectric on the thin film; forming a via opening on the second dielectric, the thin film and extending into the first dielectric; forming a line trench on a portion of the second dielectric; and filling the via opening and the line trench with a conductive material for forming a contact via and a contact line, where the contact via is partially embedded in the interconnect element.Type: GrantFiled: November 18, 2010Date of Patent: June 18, 2013Assignee: International Business Machines CorporationInventors: Birendra Agarwala, Du Nguyen, Hazara Rathore
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Publication number: 20110117737Abstract: A metal interconnect structure in ultra low-k dielectrics is described having a capped interconnect layer; an interconnect feature with a contact via and a contact line formed in a dielectric layer, where the via is partially embedded into the interconnect layer; and a thin film formed on the dielectric layer and separating the dielectric layer from the contact line. A method of fabricating the interconnect structure is also described and includes forming a first dielectric on a capped interconnect element; forming a thin film over the first dielectric; forming a second dielectric on the thin film; forming a via opening on the second dielectric, the thin film and extending into the first dielectric; forming a line trench on a portion of the second dielectric; and filling the via opening and the line trench with a conductive material for forming a contact via and a contact line, where the contact via is partially embedded in the interconnect element.Type: ApplicationFiled: November 18, 2010Publication date: May 19, 2011Inventors: Birendra Agarwala, Du Nguyen, Hazara Rathore
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Publication number: 20100176513Abstract: A metal interconnect structure in ultra low-k dielectrics is described having a capped interconnect layer; an interconnect feature with a contact via and a contact line formed in a dielectric layer, where the via is partially embedded into the interconnect layer; and a thin film formed on the dielectric layer and separating the dielectric layer from the contact line. A method of fabricating the interconnect structure is also described and includes forming a first dielectric on a capped interconnect element; forming a thin film over the first dielectric; forming a second dielectric on the thin film; forming a via opening on the second dielectric, the thin film and extending into the first dielectric; forming a line trench on a portion of the second dielectric; and filling the via opening and the line trench with a conductive material for forming a contact via and a contact line, where the contact via is partially embedded in the interconnect element.Type: ApplicationFiled: January 9, 2009Publication date: July 15, 2010Applicant: International Business Machines CorporationInventors: Birendra Agarwala, Du Nguyen, Hazara Rathore
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Patent number: 7692439Abstract: A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate.Type: GrantFiled: May 22, 2008Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Kaushik Chanda, Birendra Agarwala, Lawrence A. Clevenger, Andrew P. Cowley, Ronald G. Filippi, Jason P. Gill, Tom C. Lee, Baozhen Li, Paul S. McLaughlin, Du B. Nguyen, Hazara S. Rathore, Timothy D. Sullivan, Chih-Chao Yang
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Patent number: 7639032Abstract: A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (?m).Type: GrantFiled: December 19, 2007Date of Patent: December 29, 2009Assignee: International Business Machines CorporationInventors: Kaushik Chanda, Birendra Agarwala, Lawrence A. Clevenger, Andrew P. Cowley, Ronald G. Filippi, Jason P. Gill, Tom C. Lee, Baozhen Li, Paul S. McLaughlin, Du B. Nguyen, Hazara S. Rathore, Timothy D. Sullivan, Chih-Chao Yang
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Publication number: 20080231312Abstract: A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate.Type: ApplicationFiled: May 22, 2008Publication date: September 25, 2008Inventors: Kaushik Chanda, Birendra Agarwala, Lawrence A. Clevenger, Andrew P. Cowley, Ronald G. Filippi, Jason P. Gill, Tom C. Lee, Baozhen Li, Paul S. McLaughlin, Du B. Nguyen, Hazara S. Rathore, Timothy D. Sullivan, Chih-Chao Yang
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Patent number: 7397260Abstract: A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (?m).Type: GrantFiled: November 4, 2005Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Kaushik Chanda, Birendra Agarwala, Lawrence A. Clevenger, Andrew P. Cowley, Ronald G. Filippi, Jason P. Gill, Tom C. Lee, Baozhen Li, Paul S. McLaughlin, Du B. Nguyen, Hazara S. Rathore, Timothy D. Sullivan, Chih-Chao Yang
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Publication number: 20080107149Abstract: A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (?m).Type: ApplicationFiled: December 19, 2007Publication date: May 8, 2008Inventors: Kaushik Chanda, Birendra Agarwala, Lawrence Clevenger, Andrew Cowley, Ronald Filippi, Jason Gill, Tom Lee, Baozhen Li, Paul McLaughlin, Du Nguyen, Hazara Rathore, Timothy Sullivan, Chih-Chao Yang
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Publication number: 20070205515Abstract: Device with a damascene interconnect for integrated circuits with improved reliability and improved electromigration properties. The device including a dual damascene line having a metal line and a via, and a redundant liner arranged to divide the metal line.Type: ApplicationFiled: May 9, 2007Publication date: September 6, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Birendra AGARWALA, Du Binh NGUYEN, Hazara RATHORE
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Publication number: 20070115018Abstract: A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (?m).Type: ApplicationFiled: November 4, 2005Publication date: May 24, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kaushik Chanda, Birendra Agarwala, Lawrence Clevenger, Andrew Cowley, Ronald Filippi, Jason Gill, Tom Lee, Baozhen Li, Paul McLaughlin, Du Nguyen, Hazara Rathore, Timothy Sullivan, Chih-Chao Yang
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Publication number: 20070111510Abstract: An interconnect structure, comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.Type: ApplicationFiled: January 4, 2007Publication date: May 17, 2007Inventors: Birendra Agarwala, Eric Coker, Anthony Correale, Hazara Rathore, Timothy Sullivan, Richard Wachnik
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Publication number: 20070111497Abstract: Device and method of fabricating device. The device includes a dual damascene line having a metal line and a via, and a redundant liner arranged to divide the metal line. The method includes forming a trench in a metal stripe of a dual damascene line, depositing a barrier layer in the trench, and filling a remainder of the trench with metal.Type: ApplicationFiled: November 15, 2005Publication date: May 17, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Birendra Agarwala, Du Binh Nguyen, Hazara Rathore
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Publication number: 20060180930Abstract: The present invention provides an interconnect structure that includes a diffusion barrier which is positioned within the structure in a fashion that increases the reliability and lifetime of the interconnect structure.Type: ApplicationFiled: February 11, 2005Publication date: August 17, 2006Applicant: International Business Machines CorporationInventors: Du Nguyen, Birendra Agarwala, Conrad Barile, Jawahar Nayak, Hazara Rathore
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Publication number: 20060014376Abstract: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material.Type: ApplicationFiled: September 20, 2005Publication date: January 19, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Birendra Agarwala, Conrad Barile, Hormazdyar Dalal, Brett Engel, Michael Lane, Ernest Levine, Xiao Liu, Vincent McGahay, John McGrath, Conal Murray, Jawahar Nayak, Du Nguyen, Hazara Rathore, Thomas Shaw