Abstract: A configuration for testing an integrated semiconductor memory having a control I/O terminal and data I/O terminals, is described, and in which case test signals are prescribed by a test unit. The configuration has a circuit inserted into the signal path between the test unit and the memory. The circuit contains a data writing device for receiving test data from the test unit and for outputting the test data to the memory, a control signal writing device for receiving test control signals of a control channel of the test unit and for outputting the test control signals to the memory, and a reading/coding device for receiving response data signals and response control signals from the memory. The reading/coding device codes the received response data signals with the response control signals and outputs the coded response signals to the test unit.

Abstract: A configuration for testing an integrated semiconductor memory having a control I/O terminal and data I/O terminals, is described, and in which case test signals are prescribed by a test unit. The configuration has a circuit inserted into the signal path between the test unit and the memory. The circuit contains a data writing device for receiving test data from the test unit and for outputting the test data to the memory, a control signal writing device for receiving test control signals of a control channel of the test unit and for outputting the test control signals to the memory, and a reading/coding device for receiving response data signals and response control signals from the memory. The reading/coding device codes the received response data signals with the response control signals and outputs the coded response signals to the test unit.