Abstract: A mother board is mounted in an electrical equipment frame and has the receptacle of a first connector attached thereto at one face. The plug of the first connector is attached to a daughter board at an interconnect edge so that the first connector can be engaged by movement of the daughter board toward the mother board along an axis perpendicular to the interconnect edge of the daughter board and to the face of the mother board. A mezzanine assembly is attached to the daughter board and includes a mezzanine board in spaced parallel relationship with the daughter board and having an edge which is substantially parallel to the interconnect edge of the daughter board and at which the receptacle of a second connector is attached to the mezzanine board. An interconnect board is mounted in the frame and has an edge at which the plug of the second connector is attached to the interconnect board.

Abstract: A crosspoint switch having M input terminals and N output terminals has (M/m) times (N/n) crosspoint switch modules each having m input conductors and n output conductors. (M/m) of the crosspoint switch modules have their input conductors connected to the M input terminals respectively of the crosspoint switch, and (N/n) of the modules have their output conductors connected to the N output terminals respectively of the crosspoint switch. The input conductors of the first module are connected to respective input conductors of a second module and the output conductors of the first module are connected to respective output conductors of a third module.

Abstract: A circuit for processing an input pulse signal of which the slew rate is dependent on pulse frequency comprises an amplifier (30; 78) for receiving the input pulse signal and generating an output pulse signal having transitions of which the slew rate is dependent on a bias current supplied to the amplifier, and a circuit (38-66; 82-108) for supplying bias current to the amplifier, the bias current being representative at least substantially of the frequency of occurrence of pulses in the input pulse signal.

Abstract: A circuit for processing an input pulse signal of which the slew rate is dependent on pulse frequency comprises an amplifier (30; 78) for receiving the input pulse signal and generating an output pulse signal having transitions of which the slew rate is dependent on a bias current supplied to the amplifier, and a circuit (38-66; 82-108) for supplying bias current to the amplifier, the bias current being representative at least substantially of the frequency of occurrence of pulses in the input pulse signal.

Abstract: A circuit board comprises a substrate, a connector part, and a mounting mechanism attaching the connector part to the substrate at an edge thereof in a manner allowing forcible movement of the connector part relative to the substrate in a direction having a component perpendicular both to its edge and to a line normal to the substrate. When the substrate is held stationary relative to a connector part that is complementary to the first-mentioned connector part and is presented toward the first-mentioned connector part, the mounting mechanism can be employed to advance the first-mentioned connector part into engagement with the complementary connector part.

Abstract: Differential amplifier apparatus comprises a summing and inverting network for developing an output signal of which the magnitude is proportional to the common mode component of an input signal received at first and second input terminals of the apparatus and of which the polarity is opposite the polarity of the common mode component. A summing network is connected to the first and second input terminals and to the output of the summing and inverting network and has first and second intermediate nodes. A first differential amplifier has a non-inverting input connected to a first intermediate node of the summing network, and a second differential amplifier has a non-inverting input connected to the second intermediate node of the summing network. A bridging resistor is connected between the inverting inputs of the first and second differential amplifiers.

Abstract: A circuit for converting ECL logic level signals to CMOS logic level signals comprises a differential amplifier defining first and second current paths that are connected to a negative reference potential level. When the ECL input signal is logical zero, the first current path is non-conductive and the second path is conductive, and vice versa when the input signal is logical one. A first transistor has its base connected to the first current path, its emitter connected to a positive reference potential level, and its collector connected to the second current path. A second transistor has its base connected to the second current path, its emitter connected to the output terminal, and its collector connected to a ground reference potential level. A pull-up resistor is connected between the collector and emitter of the first transistor.

Abstract: A switch for selectively routing a signal to a receiving device for interrupting the transmission of said signal to said receiving device includes two latches, a differential delay circuit, and a buffer amplifier. State commands to individual switches in a routing system can be preset asynchronously by one latch and all of the switches in the system can be enabled to change states simultaneously by triggering a second latch. The switch is also of the make before break type, i.e., it turns on more rapidly than it turns off. The switch also includes programmable current sources in the buffer amplifier stage. These current sources are programmable to provide full power when the switch is conducting and to provide only standby power when the switch is nonconductive.

Abstract: A current mirror which is stable and accurate for a broad range of beta gain factors of the individual transistors thereof has two transistors of one type connected substantially as a Darlington pair. A multiplying, multi-collector transistor of the opposite type is connected serially between the collectors of the Darlington pair from base to emitter. One collector is diode connected to the base and the other is returned to a potential source. The collectors are of equal area.

Abstract: A video signal that is representative of a wide scene comprises signal elements corresponding to a plurality of horizontal line intervals of a raster. A luminance component and two chrominance components are included in each horizontal line interval, in time-compressed sequential relationship. The video signal also incorporates information representative of a number in the range from zero to the difference between the aspect ratio of the wide scene and the aspect ratio of a scene represented by a conventional video signal format. This information determines the portion of the wide scene that is represented by a video signal of the conventional format derived from the video signal representative of the wide scene.

Abstract: A circuit for converting ECL logical signals into TTL logical signals comprises a differential amplifier defining two current paths leading to a negative reference potential source. When the ECL input signal is logical zero, the first current path is closed and the second current path is open, and vice versa when the input signal is logical one. A first transistor has its base connected to the first current path and its emitter connected to a positive reference potential source, and is biased by a load resistor connected to the first current path. A second transistor has its emitter connected to the collector of the first transistor and its base connected to the second current path, and is biased by a second resistor. When the input ECL signal is logical one, the first current path is open and the first and second transistors are on and off respectively, the potential at the output terminal of the circuit being limited by a clamping diode connected between the base and collector of the first transistor.

Abstract: A circuit receives an input logical signal of one polarity and converts it into two balanced logical output signals of the opposite polarity. The circuit comprises two resistors connected between a reference potential source of the polarity of the output signals and the terminals at which the output signals are provided. The circuit also comprises a current source. Each resistor has a resistance value such that when it is traversed by the current from the current source the potential difference between its ends is equal to the difference between the two possible potential levels of the output signals. A differential switching device responds to the input signal being at a first potential level by connecting one of the output terminals to the current source and isolating the other output terminal from the current source, and vice versa when the input signal is at a second potential level.

Abstract: An electronic circuit which produces controlled rise and fall times with a sine-squared step pulse shape from rectangular input pulses is disclosed. The circuit uses the inherent nonlinear behavior of a bipolar transistor differential pair to shape the pulses and requires very little passive filtering. The output wave-shaped current may be developed across a resistor or fed to the input mode of a feedback amplifier.

Abstract: A circuit for reducing the effects of negative-going impulse noise in composite television video signals has on sync separators is disclosed. A variable output current source is used to supply rundown current to a dc restorer in a sync separator. A retriggerable monostable multivibrator is triggered by negative-going impulse spikes in the composite video signal. The output of this multivibrator is coupled to the current source to increase its output and therefore decrease the time required for the dc restorer to recover from the negative spike.

Abstract: An apparatus and method for precise separation of synchronizing information from a color television signal is described. Synchronizing signals are separated from the input video and used in a sample-and-hold circuit as the sampling pulses. The input video is sampled during the duration of the sync pulse. The sample is inverted and fed to a summing point where it is summed with a delayed version of the input video. A null is produced at the summing point during the duration of the input sync pulse. Since the input video to summing point has been delayed, the clamp null at the summing point begins during the front porch of the horizontal line interval allowing the leading edge of sync to be picked off very accurately by a sync separating comparator.