Abstract: A method for manufacturing a wide band gap semiconductor device using a substrate of SiC wafer is disclosed. The method includes coating the substrate with a hard mask material, performing lithography to define patterned openings in the hard mask material of the substrate, etching the substrate to form patterned trenches from the defined patterned openings, removing the hard mask using a chemical process from the substrate, cleaning the substrate with the patterned trenches, performing epitaxy on the substrate to form a uniform single crystal layer over the patterned trenches to create a plurality of micro voids, kiss polishing the substrate, performing another epitaxy on the substrate using a fast epitaxial growth process to provide an active device epitaxial layer suitable to fabricate SiC devices, and after fabrication of the SiC devices, severing the plurality of micro voids to extract the SiC devices from the substrate of the SiC wafer.

Abstract: Technologies are generally described for increase of spacing between source and drain regions of a vertical high voltage transistor without a significant corresponding increase in the die size. In some examples, active silicon (at drain potential) may be removed at an edge of the die in the scribe grid so that the active silicon is approximately below a surface of the edge termination formed by a region of deep dielectric filled trenches. The recessed drain region at the edge of the die may increase a flashover distance without appreciably increasing the die size. Thus, a distance between the recessed drain region and the surface source region may be increased by a combination of vertical and lateral spacing resulting in a smaller overall die size and smaller parasitic capacitances when operated with substantially the same operating voltage.

Abstract: Technologies are generally described for increase of spacing between source and drain regions of a vertical high voltage transistor without a significant corresponding increase in the die size. In some examples, active silicon (at drain potential) may be removed at an edge of the die in the scribe grid so that the active silicon is approximately below a surface of the edge termination formed by a region of deep dielectric filled trenches. The recessed drain region at the edge of the die may increase a flashover distance without appreciably increasing the die size. Thus, a distance between the recessed drain region and the surface source region may be increased by a combination of vertical and lateral spacing resulting in a smaller overall die size and smaller parasitic capacitances when operated with substantially the same operating voltage.

Abstract: The invention relates to inter-level realignment after a stage of epitaxy on a face (31) of a substrate (30), comprising the production of at least one initial guide mark (32) on the face of the substrate, this initial guide mark being designed so as to be transferred, during epitaxy, onto the surface of the epitaxied layer (36). The initial guide mark (32) is produced in such a way that, during epitaxy, its edges create growth defects that propagate as far as the surface of the epitaxied layer (36) to provide a transferred guide mark (37) on the surface of the epitaxied layer (36) reproducing the shape of the initial guide mark (32) and in alignment with the initial guide mark.

Abstract: A microelectronic assembly and a method for forming the same are provided. The method includes forming first and second lateral etch stop walls (44, 46) in a semiconductor substrate (20) having first and second opposing surfaces (22, 24). An inductor (56) is formed on the first surface (22) of the semiconductor substrate (20) and a hole (60) is formed through the second surface (24) of the substrate (20) to expose the substrate (20) between the first and second lateral etch stop walls (44, 46). The substrate (20) is isotropically etched between the first and second lateral etch stop walls (44, 46) through the etch hole (60) to create a cavity 62) within the semiconductor substrate (20). A sealing layer (70) is formed over the etch hole (60) to seal the cavity (62).

Abstract: A bimorphic structure responsive to changes in an environmental condition, sensor structures incorporating one or more of such bimorphic structures, and a method of forming such bimorphic structures. The sensor structure has an electrically-conductive first contact on a substrate, and a bimorph beam anchored to the substrate so that a portion thereof is suspended above the first contact. The bimorph beam has a multilayer structure that includes first and second layers, with the second layer between the first layer and the substrate. A portion of the first layer projects through an opening in the second layer toward the first contact so as to define an electrically-conductive second contact located on the beam so as to be spaced apart and aligned with the first contact for contact with the first contact when the beam sufficiently deflects toward the substrate.

Abstract: A capacitive pressure sensor and method for its fabrication. The sensor is fabricated from first and second wafers to have a mechanical capacitor comprising a fixed electrode and a moving electrode defined by a conductive plate. The sensor further has a diaphragm on a surface of the first wafer that is mechanically coupled but electrically insulated from the conductive plate. A conductive layer on the surface of the first wafer is spaced apart from the conductive plate to define the fixed electrode. The second wafer is bonded to the first wafer and carries interface circuitry for the sensor, including the conductive plate and the fixed electrode which are between the first and second wafers and electrically connected to the interface circuitry. At least an opening is present in the first wafer and its first conductive layer by which the diaphragm is released and exposed to an environment surrounding the sensor.

Abstract: A three-axis inertial sensor and a process for its fabrication using an silicon-on-oxide (SOI) wafer as a starting material. The SOI wafer has a first conductive layer separated from a second conductive layer by an insulative buried oxide (BOX) layer. The SOI wafer is fabricated to partially define in its first conductive layer at least portions of proof masses for z, x, and y-axis sensing devices of the sensor. After a conductive deposited layer is deposited and patterned to form a suspension spring for the proof mass of the z-axis sensing device, the SOI wafer is bonded to a substrate that preferably carries interface circuitry for the z, x, and y-axis devices, with the SOI wafer being oriented so that its first conductive layer faces the substrate. Portions of the BOX layer are then etched to fully release the proof masses.

Abstract: A method of forming a semiconductor component (100) having an active semiconductor device (680) above a passive device (470) includes providing a semiconductor wafer (110) having an upper surface (115), forming a trench (216) in the upper surface of the semiconductor wafer, forming a cavity (317) in the semiconductor wafer below the trench, forming the passive device in the cavity; and forming at least a portion of the active semiconductor device in the semiconductor wafer and above the passive device.

Abstract: The invention relates to inter-level realignment after a stage of epitaxy on a face (31) of a substrate (30), comprising the production of at least one initial guide mark (32) on the face of the substrate, this initial guide mark being designed so as to be transferred, during epitaxy, onto the surface of the epitaxied layer (36). The initial guide mark (32) is produced in such a way that, during epitaxy, its edges create growth defects that propagate as far as the surface of the epitaxied layer (36) to provide a transferred guide mark (37) on the surface of the epitaxied layer (36) reproducing the shape of the initial guide mark (32) and in alignment with the initial guide mark.

Abstract: Methods are provided for forming an electronic assembly (54). At least one depression (38) is formed in a surface of a substrate (20). A contact formation (44) is placed in the depression. A microelectronic die (46) is attached to the substrate using the contact formation. An electronic assembly is also provided. The invention further provides an electronic assembly. The electronic assembly includes a substrate having a plurality of depressions formed thereon, a microelectronic die having a microelectronic device formed therein, and a plurality of contact formations bonded to and interconnecting the substrate and the microelectronic die. Each of the contact formations are positioned within a respective depression on the substrate.

Abstract: A MEMS device and method of fabrication including a plurality of structural tie bars for added structural integrity. The MEMS device includes an active layer and a substrate having an insulating material formed therebetween, first and second pluralities of stationary electrodes and a plurality of moveable electrodes in the active layer. A plurality of interconnects are electrically coupled to a second surface of each of the first and second pluralities of stationary electrodes. A plurality of anchors fixedly attach a first surface of each of the first and second pluralities of stationary electrodes to the substrate. A first structural tie bar couples a second surface of each of the first plurality of stationary electrodes and a second structural tie bar couples a second surface of each of the second plurality of stationary electrodes.

Abstract: According to one aspect of the present invention, a method is provided for forming a microelectronic assembly. The method comprises forming first and second trenches on a semiconductor substrate, filling the first and second trenches with an etch stop material, forming an inductor on the semiconductor substrate, forming an etch hole in at least one of the etch stop layer and the semiconductor substrate to expose the substrate between the first and second trenches, isotropically etching the substrate between the first and second trenches through the etch hole to create a cavity within the substrate, and forming a sealing layer over the etch hole to seal the cavity.

Abstract: A microelectronic assembly and a method for forming the same are provided. The method includes forming first and second lateral etch stop walls in a semiconductor substrate having first and second opposing surfaces. An inductor is formed on the first surface of the semiconductor substrate and a hole is formed through the second surface of the substrate to expose the substrate between the first and second lateral etch stop walls. The substrate is isotropically etched between the first and second lateral etch stop walls through the etch hole to create a cavity within the semiconductor substrate. A sealing layer is formed over the etch hole to seal the cavity.

Abstract: The movement and mixing of microdroplets through microchannels is described employing microscale devices, comprising microdroplet transport channels, reaction regions, electrophoresis modules, and radiation detectors. The discrete droplets are differentially heated and propelled through etched channels. Electronic components are fabricated on the same substrate material, allowing sensors and controlling circuitry to be incorporated in the same device.

Abstract: Methods have been provided for forming both wide and narrow trenches on a high-aspect ratio microelectromechanical (MEM) device on a substrate including a substrate layer (126), an active layer (128), and a first sacrificial layer (130) disposed at least partially therebetween. The method includes the steps of forming a first trench (154), a second trench (156), and a third trench (152) in the active layer (128), each trench (154, 156, 152) having an opening and sidewalls defining substantially equal first trench widths, depositing oxide and sacrificial layers thereover and removing the oxide and sacrificial layers to expose the third trench (152) and form a fourth trench (190) in the active layer (128) from the first and the second trench (154, 156), the fourth trench (190) having sidewalls defining a second trench width that is greater than the first trench width.

Abstract: A method for creating a semiconductor structure is provided. In accordance with the method, a semiconductor substrate (101) is provided over which is disposed a sacrificial layer (103), and which has a thin single crystal semiconductor layer (105) disposed over the sacrificial layer (103). An opening (107) is then created which extends through the semiconductor layer (105) and into the sacrificial layer (103). The semiconductor layer (105) is then epitaxially grown to a suitable device thickness, thereby resulting in a device layer. The semiconductor layer is grown such that the resulting device layer extends over the opening (107), and such that the surface of the portion of the device layer extending over the opening is single crystal silicon.

Abstract: Methods and apparatus are provided forming a plurality of semiconductor devices on a single substrate, and sealing two or more of the devices at different pressures. First and second semiconductor devices, each having a cavity formed therein, are formed on the same substrate. The cavity in the first device is sealed at a first pressure, and the cavity in the second device is sealed at a second pressure.

Abstract: A microelectromechanical (MEM) device includes a substrate, a structure, a travel stop, and a protective cap. The substrate has a surface, and the structure is coupled to, and movably suspended above, the substrate surface. The structure has at least an outer surface, and the travel stop coupled to the structure outer surface and movable therewith. The travel stop includes at least an inner peripheral surface that defines a cavity. The protective cap is coupled to the substrate and includes a stop section that is disposed at least partially within the travel stop cavity and is spaced apart from the travel stop inner peripheral surface. The travel stop and the protective cap stop section together limit movement of the structure in at least three orthogonal axes.

Abstract: A method of making a microelectromechanical (MEM) device using a standard silicon wafer, rather than an SOI wafer, includes selectively implanting a dopant in regions of the standard wafer, to thereby form heavily doped regions therein. The heavily doped regions are then converted to porous silicon regions. An electrical isolation layer is selectively deposited on the wafer and over a portion of one or more of the porous silicon regions. An epitaxial layer is grown over the porous silicon regions and the electrical isolation area, and device elements are formed in the epitaxial layer. Thereafter, at least portions of the porous silicon regions are removed, to thereby release the formed device elements.