Patents by Inventor Bishnu P. Das

Bishnu P. Das has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Testing integrated circuits during split fabrication
    Patent number: 10393796
    Abstract: In one aspect, a method comprises providing at least two identical front-end-of-line (FEOL) portions of an integrated circuit (IC) in a single wafer, with at least some of each FEOL portion comprising a plurality of circuit elements; building a design back-end-of-line (BEOL) portion of the IC on at least one of the FEOL portions to form a product chip, with the design BEOL portion configuring design-type interconnections of the same plurality of circuit elements for a first instantiation; building a test-only BEOL structure on at least one of the FEOL portions to form a sacrificial test device, with the test-only BEOL structure configuring test-type interconections of the same plurality of circuit elements for a second instantiation; and testing the sacrificial test device for at least one of functionality or reliability.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: August 27, 2019
    Assignee: Carnegie Mellon University
    Inventors: Lawrence Pileggi, Bishnu P. Das, Kaushik Vaidyanathan
  • TESTING INTEGRATED CIRCUITS DURING SPLIT FABRICATION
    Publication number: 20160341786
    Abstract: In one aspect, a method comprises providing at least two identical front-end-of-line (FEOL) portions of an integrated circuit (IC) in a single wafer, with at least some of each FEOL portion comprising a plurality of circuit elements; building a design back-end-of-line (BEOL) portion of the IC on at least one of the FEOL portions to form a product chip, with the design BEOL portion configuring design-type interconnections of the same plurality of circuit elements for a first instantiation; building a test-only BEOL structure on at least one of the FEOL portions to form a sacrificial test device, with the test-only BEOL structure configuring test-type interconections of the same plurality of circuit elements for a second instantiation; and testing the sacrificial test device for at least one of functionality or reliability.
    Type: Application
    Filed: January 21, 2015
    Publication date: November 24, 2016
    Inventors: Lawrence Pileggi, Bishnu P. Das, Kaushik Vaidyanathan