Abstract: Authenticity of Artificial Intelligence (AI) results may be verified by creating, for an AI system, from a plurality of original inputs to form a plurality of original inference results, a plurality of original signatures of representative elements of an internal state of the AI system constructed from each individual original inference result of the plurality of original inference results. During deployment of the AI system, a matching of a plurality of deployment time inference results with a plurality of deployment time signatures, to the plurality of original signatures and the plurality of original inference results, may be verified.

Abstract: Authenticity of Artificial Intelligence (AI) results may be verified by creating, for an AI system, from a plurality of original inputs to form a plurality of original inference results, a plurality of original signatures of representative elements of an internal state of the AI system constructed from each individual original inference result of the plurality of original inference results. During deployment of the AI system, a matching of a plurality of deployment time inference results with a plurality of deployment time signatures, to the plurality of original signatures and the plurality of original inference results, may be verified.

Abstract: A model-based virtual power management driven multi-chip system simulator generates utilization data and performance data with a workload model that models one or more types of workloads based on parameters that characterize the one or more types of workloads. The simulator generates thermal data and power consumption data with a power model that models power consumption at a chip-level and a system-level. The simulator then generates performance counter information with a performance model that models change of performance counters over time and at least one of the generated utilization data and the generated performance data as input to the performance model. The simulator provides this generated data as input to a driver of the simulator.

Abstract: A model-based virtual power management driven multi-chip system simulator generates utilization data and performance data with a workload model that models one or more types of workloads based on parameters that characterize the one or more types of workloads. The simulator generates thermal data and power consumption data with a power model that models power consumption at a chip-level and a system-level. The simulator then generates performance counter information with a performance model that models change of performance counters over time and at least one of the generated utilization data and the generated performance data as input to the performance model. The simulator provides this generated data as input to a driver of the simulator.

Abstract: A model-based virtual power management driven multi-chip system simulator generates utilization data and performance data with a workload model that models one or more types of workloads based on parameters that characterize the one or more types of workloads. The simulator generates thermal data and power consumption data with a power model that models power consumption at a chip-level and a system-level. The simulator then generates performance counter information with a performance model that models change of performance counters over time and at least one of the generated utilization data and the generated performance data as input to the performance model. The simulator provides this generated data as input to a driver of the simulator.

Abstract: Associating processor and processor core energy consumption with a task such as a virtual machine is disclosed. Various events cause a trace record to be written to a trace buffer for a processor. An identifier associated with a task using a processor core of the processor is read. In addition, one or more values associated with an energy consumption of the processor core are read. In response to the event, the one or more values associated with the energy consumption of the processor core and the identifier are written to the trace buffer memory.

Abstract: Embodiments include receiving, at a microcontroller of a chip, a request to execute a first task having a first priority. Embodiments further include determining that a second task having a second priority is currently executing. Embodiments further include determining that the first priority is higher than the second priority. Embodiments further include determining whether a value in a register indicates that the second task can be interrupted. If it is determined that the second task can be interrupted, embodiments further include triggering execution of the second task. If it is determined that the second task cannot be interrupted, embodiments further include waiting for lapse of a time period since receipt of the request to execute the first task, and interrupting the second task upon detecting lapse of the time period, or detecting, prior to the lapse of the time period, that the second task can be interrupted.

Abstract: Embodiments include an apparatus comprising a processor and a computer readable storage medium having computer usable program code. The computer usable program code can be configured to determine whether priority of a requested task is higher than a priority of a currently executing task. The computer usable program code can be further configured to determine whether a value indicates that the currently executing task can be interrupted. The computer usable program code can be configured to trigger execution of the requested task on the processor, if the value indicates that the currently executed task can be interrupted. The computer usable program code can be further configured to wait for lapse of a time period and, interrupt the currently executing task upon detection of lapse of the time period or detection of a change to the value, if the value indicates that the currently executing task cannot be interrupted.

Abstract: Computing system voltage control methods include receiving an indication of a first performance state. The first performance state is associated with a first voltage and applies to at least one computing system component. The indication of the first performance state is received by a first computing system component from a second computing system component. An indication of a second performance state is received, wherein the second performance state is associated with a second voltage that is not equal to the first voltage. It is determined whether the second performance state is within a range defined by a minimum performance state and a maximum performance state. Responsive to determining that the second performance state is within the range defined by the minimum performance state and the maximum performance state, the voltage of the at least one computing system component is set equal to the voltage associated with the second performance state.

Abstract: An indication of a first performance state is received, the first performance state being associated with a first voltage. The first performance state applies to at least one computing system component and the indication is received by a computing system component distinct from the requesting computing system component. An indication of a second performance state is received. The second performance state is associated with a second voltage that is different from the first voltage. It is determined whether the second performance state is within a range defined by a minimum and maximum performance state. Responsive to a determination that the second performance state is within the minimum and maximum performance state, the voltage of the at least one computing system component is set equal to the voltage associated with the second performance state.

Abstract: Associating processor and processor core energy consumption with a task such as a virtual machine is disclosed. Various events cause a trace record to be written to a trace buffer for a processor. An identifier associated with a task using a processor core of the processor is read. In addition, one or more values associated with an energy consumption of the processor core are read. In response to the event, the one or more values associated with the energy consumption of the processor core and the identifier are written to the trace buffer memory.

Abstract: Associating processor and processor core energy consumption with a task such as a virtual machine is disclosed. Various events cause a trace record to be written to a trace buffer for a processor. An identifier associated with a task using a processor core of the processor is read. In addition, one or more values associated with an energy consumption of the processor core are read. In response to the event, the one or more values associated with the energy consumption of the processor core and the identifier are written to the trace buffer memory.

Abstract: A maximum and a minimum performance operating limit is set for a plurality of processing units in accordance with a set of one or more rules enforced by the performance supervisor. Each of the plurality of processing units has logic configured to ensure a request for an operational setting complies with the maximum and minimum operating limits. Each of the plurality of processing units is configured to output a request for a limit compliant operational setting to a performance controller. The performance controller is configured to actuate the operational request.

Abstract: An apparatus includes memory, a processor coupled to the memory, and a set of one or more frequency target monitors. The processor includes a set of one or more processor cores, and the set of one or more frequency target monitors are coupled to the set of one or more processor cores. Each frequency target monitor is configured to determine a difference between an actual performance and an expected performance of a processor core from the set of one or more processor cores. Each frequency target monitor is also configured to, responsive to determining the difference between the actual performance and the expected performance of the processor core from the set of one or more processor cores, record an indication of a difference between the actual performance and the expected performance of the processor core from the set of one or more processor cores.

Abstract: Embodiments of the inventive subject matter include setting minimum and maximum performance operating limits for each of a plurality of controllers. The operating limits are set in accordance with performance rules imposed on the system. In response to a request to change operation of a processing unit to a requested operational setting, it is determined whether the requested operational setting complies with the minimum and maximum performance operating limits. The minimum performance operating limit is sent to a performance controller if the requested operational setting does not comply with the minimum performance operating limit. The maximum performance operating limit is sent to a performance controller if the requested operational setting does not comply with the maximum performance operating limit. The requested operational setting is sent to a performance controller if the requested operational setting complies with the minimum and maximum performance operating limits.

Abstract: A model-based virtual power management driven multi-chip system simulator generates utilization data and performance data with a workload model that models one or more types of workloads based on parameters that characterize the one or more types of workloads. The simulator generates thermal data and power consumption data with a power model that models power consumption at a chip-level and a system-level. The simulator then generates performance counter information with a performance model that models change of performance counters over time and at least one of the generated utilization data and the generated performance data as input to the performance model. The simulator provides this generated data as input to a driver of the simulator.

Abstract: A model-based virtual power management driven multi-chip system simulator generates utilization data and performance data with a workload model that models one or more types of workloads based on parameters that characterize the one or more types of workloads. The simulator generates thermal data and power consumption data with a power model that models power consumption at a chip-level and a system-level. The simulator then generates performance counter information with a performance model that models change of performance counters over time and at least one of the generated utilization data and the generated performance data as input to the performance model. The simulator provides this generated data as input to a driver of the simulator.

Abstract: Embodiments include an apparatus comprising a processor and a computer readable storage medium having computer usable program code. The computer usable program code can be configured to determine whether priority of a requested task is higher than a priority of a currently executing task. The computer usable program code can be further configured to determine whether a value indicates that the currently executing task can be interrupted. The computer usable program code can be configured to trigger execution of the requested task on the processor, if the value indicates that the currently executed task can be interrupted. The computer usable program code can be further configured to wait for lapse of a time period and, interrupt the currently executing task upon detection of lapse of the time period or detection of a change to the value, if the value indicates that the currently executing task cannot be interrupted.

Abstract: Embodiments include receiving, at a microcontroller of a chip, a request to execute a first task having a first priority. Embodiments further include determining that a second task having a second priority is currently executing. Embodiments further include determining that the first priority is higher than the second priority. Embodiments further include determining whether a value in a register indicates that the second task can be interrupted. If it is determined that the second task can be interrupted, embodiments further include triggering execution of the second task. If it is determined that the second task cannot be interrupted, embodiments further include waiting for lapse of a time period since receipt of the request to execute the first task, and interrupting the second task upon detecting lapse of the time period, or detecting, prior to the lapse of the time period, that the second task can be interrupted.

Abstract: Embodiments of the inventive subject matter include setting minimum and maximum performance operating limits for each of a plurality of controllers. The operating limits are set in accordance with performance rules imposed on the system. In response to a request to change operation of a processing unit to a requested operational setting, it is determined whether the requested operational setting complies with the minimum and maximum performance operating limits. The minimum performance operating limit is sent to a performance controller if the requested operational setting does not comply with the minimum performance operating limit. The maximum performance operating limit is sent to a performance controller if the requested operational setting does not comply with the maximum performance operating limit. The requested operational setting is sent to a performance controller if the requested operational setting complies with the minimum and maximum performance operating limits.