Patents by Inventor Biswajeet Guha

Biswajeet Guha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200006478
    Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: William Hsu, Biswajeet Guha, Leonard Guler, Souvik Chakrabarty, Jun Sung Kang, Bruce Beattie, Tahir Ghani
  • Publication number: 20200006525
    Abstract: Integrated circuit structures including increased transistor source/drain (S/D) contact area using a sacrificial S/D layer are provided herein. The sacrificial layer, which includes different material from the S/D material, is deposited into the S/D trenches prior to the epitaxial growth of that S/D material, such that the sacrificial layer acts as a space-holder below the S/D material. During S/D contact processing, the sacrificial layer can be selectively etched relative to the S/D material to at least partially remove it, leaving space below the S/D material for the contact metal to fill. In some cases, the contact metal is also between portions of the S/D material. In some cases, the contact metal wraps around the epi S/D, such as when dielectric wall structures on either side of the S/D region are employed. By increasing the S/D contact area, the contact resistance is reduced, thereby improving the performance of the transistor device.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: DAX M. CRUM, BISWAJEET GUHA, WILLIAM HSU, STEPHEN M. CEA, TAHIR GHANI
  • Publication number: 20190393352
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: Biswajeet GUHA, William HSU, Leonard P. GULER, Dax M. CRUM, Tahir GHANI
  • Publication number: 20190393351
    Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-?”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 26, 2019
    Applicant: INTEL CORPORATION
    Inventors: Bruce E. Beattie, Leonard Guler, Biswajeet Guha, Jun Sung Kang, William Hsu
  • Publication number: 20190393350
    Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.
    Type: Application
    Filed: June 20, 2018
    Publication date: December 26, 2019
    Applicant: INTEL CORPORATION
    Inventors: Erica J. Thompson, Aditya Kasukurti, Jun Sung Kang, Kai Loon Cheong, Biswajeet Guha, William Hsu, Bruce Beattie
  • Publication number: 20190355811
    Abstract: A semiconductor device is described that includes a first semiconductor layer conformally disposed on at least a portion of a source region and a second semiconductor layer conformally disposed on at least a portion of a drain region between the source/drain regions and corresponding gate spacers. The semiconductor layer can prevent diffusion and/or segregation of dopants from the source and drain regions into the gate spacers of the gate stack. Maintaining the intended location of dopant atoms in the source region and drain region improves the electrical characteristics of the semiconductor device including the external resistance (“Rext”) of the semiconductor device.
    Type: Application
    Filed: May 18, 2018
    Publication date: November 21, 2019
    Applicant: INTEL CORPORATION
    Inventors: Rishabh Mehandru, Anupama Bowonder, Biswajeet Guha, Tahir Ghani, Stephen M. Cea, William Hsu, SZUYA S. LIAO, PRATIK A. PATEL
  • Patent number: 10295739
    Abstract: Methods, systems, and devices are disclosed for implementing athermal optical devices based on composite structures having different components with different thermal properties such as a composite structure having materials of positive and negative thermo-optic effects or a composite structure having materials exhibiting different thermal expansion coefficients.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: May 21, 2019
    Assignee: Cornell University
    Inventors: Michal Lipson, Biswajeet Guha
  • Publication number: 20190139957
    Abstract: Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.
    Type: Application
    Filed: July 1, 2016
    Publication date: May 9, 2019
    Inventors: Szuya S. LIAO, Biswajeet GUHA, Tahir GHANI, Christopher N. KENYON, Leonard P. GULER
  • Publication number: 20190019891
    Abstract: A trench is formed in an insulating layer to expose a native fin on a substrate. A replacement fin is deposited on the native fin in the trench. The replacement fin is trimmed laterally.
    Type: Application
    Filed: March 30, 2016
    Publication date: January 17, 2019
    Inventors: Glenn A. GLASS, Anand S. MURTHY, Karthik JAMBUNATHAN, Chandra S. MOHAPATRA, Hei KAM, Nabil G. MISTKAWI, Jun Sung KANG, Biswajeet GUHA
  • Publication number: 20180188454
    Abstract: Methods, systems, and devices are disclosed for implementing a fiber-waveguide evanescent coupling. In one aspect, a device having integrated photonic components includes a substrate, a waveguide formed on the substrate to include a terminal waveguide portion that terminates at one side of the substrate, and a fiber including a fiber core and fiber cladding surrounding the fiber core, in which at least a portion of the fiber cladding is removed at or near a fiber terminal end to enable optical evanescent coupling via a side surface of the fiber core at the or near the fiber terminal end, the fiber core at the or near the fiber terminal end is placed over the one side of the substrate to be above and to overlap with the terminal waveguide portion of the waveguide to enable optical evanescent coupling via side surfaces of the fiber core and the waveguide.
    Type: Application
    Filed: August 28, 2017
    Publication date: July 5, 2018
    Applicant: Cornell University
    Inventors: Michal Lipson, Biswajeet Guha
  • Patent number: 9746612
    Abstract: Methods, systems, and devices are disclosed for implementing a fiber-waveguide evanescent coupling. In one aspect, a device having integrated photonic components includes a substrate, a waveguide formed on the substrate to include a terminal waveguide portion that terminates at one side of the substrate, and a fiber including a fiber core and fiber cladding surrounding the fiber core, in which at least a portion of the fiber cladding is removed at or near a fiber terminal end to enable optical evanescent coupling via a side surface of the fiber core at the or near the fiber terminal end, the fiber core at the or near the fiber terminal end is placed over the one side of the substrate to be above and to overlap with the terminal waveguide portion of the waveguide to enable optical evanescent coupling via side surfaces of the fiber core and the waveguide.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: August 29, 2017
    Assignee: Cornell University
    Inventors: Michal Lipson, Biswajeet Guha
  • Publication number: 20160077282
    Abstract: Methods, systems, and devices are disclosed for implementing a fiber-waveguide evanescent coupling. In one aspect, a device having integrated photonic components includes a substrate, a waveguide formed on the substrate to include a terminal waveguide portion that terminates at one side of the substrate, and a fiber including a fiber core and fiber cladding surrounding the fiber core, in which at least a portion of the fiber cladding is removed at or near a fiber terminal end to enable optical evanescent coupling via a side surface of the fiber core at the or near the fiber terminal end, the fiber core at the or near the fiber terminal end is placed over the one side of the substrate to be above and to overlap with the terminal waveguide portion of the waveguide to enable optical evanescent coupling via side surfaces of the fiber core and the waveguide.
    Type: Application
    Filed: April 21, 2014
    Publication date: March 17, 2016
    Inventors: Michal Lipson, Biswajeet Guha
  • Publication number: 20160070062
    Abstract: Methods, systems, and devices are disclosed for implementing athermal optical devices based on composite structures having different components with different thermal properties such as a composite structure having materials of positive and negative thermo-optic effects or a composite structure having materials exhibiting different thermal expansion coefficients.
    Type: Application
    Filed: April 22, 2014
    Publication date: March 10, 2016
    Inventors: Michal Lipson, Biswajeet Guha
  • Patent number: 8457453
    Abstract: Apparatus and methods that compensate for the thermally-induced drift of the resonance frequency of a closed-loop resonator include, in an exemplary embodiment, a waveguide-based Mach-Zehnder interferometer (MZI) and an overcoupled, waveguide-based microring resonator. The temperature-induced red-shifting ring resonance can be balanced by a spectral blueshift with temperature of the MZI. To stabilize the resonance of the ring at a given wavelength, the change in optical path lengths with temperature of the ring and the MZI should be equal and opposite. The interplay of nonlinear change in phase of ring resonator with temperature and linear change in phase of MZI with temperature, along with matching the period of this phase change, gives rise to perfect oscillation in the combined system resonance with temperature.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: June 4, 2013
    Assignee: Cornell University
    Inventors: Michal Lipson, Biswajeet Guha
  • Publication number: 20110102804
    Abstract: Apparatus and methods that compensate for the thermally-induced drift of the resonance frequency of a closed-loop resonator include, in an exemplary embodiment, a waveguide-based Mach-Zehnder interferometer (MZI) and an overcoupled, waveguide-based microring resonator. The temperature-induced red-shifting ring resonance can be balanced by a spectral blueshift with temperature of the MZI. To stabilize the resonance of the ring at a given wavelength, the change in optical path lengths with temperature of the ring and the MZI should be equal and opposite. The interplay of nonlinear change in phase of ring resonator with temperature and linear change in phase of MZI with temperature, along with matching the period of this phase change, gives rise to perfect oscillation in the combined system resonance with temperature.
    Type: Application
    Filed: November 1, 2010
    Publication date: May 5, 2011
    Applicant: CORNELL UNIVERSITY
    Inventors: Michal Lipson, Biswajeet Guha