Patents by Inventor Biswajit Sur
Biswajit Sur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11770982Abstract: In a general aspect, an integrated quantum circuit includes a first substrate and a second substrate. The first substrate includes a first surface and a recess formed in the first substrate along the first surface. The recess has a recess surface and is configured to enclose a quantum circuit element. The first substrate includes a first electrically-conductive layer disposed on the first surface and covering at least a portion of the recess surface. The first electrically-conductive layer includes a first superconducting material. The second substrate includes a second surface and a quantum circuit element. The second substrate includes a second electrically-conductive layer on the second surface that includes a second superconducting material. The first substrate is adjacent the second substrate to enclose the quantum circuit device within the recess. The first electrically-conductive layer of the first substrate is electrically-coupled to the second electrically-coupled layer of the second substrate.Type: GrantFiled: August 9, 2021Date of Patent: September 26, 2023Assignee: Rigetti & Co, LLCInventors: Jayss Daniel Marshall, Chih-Yang Li, Biswajit Sur, Nagesh Vodrahalli, Mehrnoosh Vahidpour, William Austin O'Brien, IV, Andrew Joseph Bestwick, Chad Tyler Rigetti, James Russell Renzas
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Patent number: 11121301Abstract: In a general aspect, an integrated quantum circuit includes a first substrate and a second substrate. The first substrate includes a first surface and a recess formed in the first substrate along the first surface. The recess has a recess surface and is configured to enclose a quantum circuit element. The first substrate includes a first electrically-conductive layer disposed on the first surface and covering at least a portion of the recess surface. The first electrically-conductive layer includes a first superconducting material. The second substrate includes a second surface and a quantum circuit element. The second substrate includes a second electrically-conductive layer on the second surface that includes a second superconducting material. The first substrate is adjacent the second substrate to enclose the quantum circuit device within the recess. The first electrically-conductive layer of the first substrate is electrically-coupled to the second electrically-coupled layer of the second substrate.Type: GrantFiled: June 19, 2018Date of Patent: September 14, 2021Assignee: Rigetti & Co, Inc.Inventors: Jayss Daniel Marshall, Chih-Yang Li, Biswajit Sur, Nagesh Vodrahalli, Mehrnoosh Vahidpour, William Austin O'Brien, IV, Andrew Joseph Bestwick, Chad Tyler Rigetti, James Russell Renzas
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Patent number: 9218041Abstract: An apparatus includes logic to control heat generation in a device. The device to operate at least in one of a first state and a second state, wherein the device to consume more power in the first state than in the second state. The device to connect to a network at least for a portion of time while in the second state. The logic to select a plurality of thermal control solutions to decrease the generation of heat in the device in the second state, the selected thermal control solution to be performed while the device is in the second state to reduce the generated heat to below a predetermined level.Type: GrantFiled: December 28, 2012Date of Patent: December 22, 2015Assignee: Intel CorporationInventors: Biswajit Sur, Thomas E. Walsh, Ajay G. Gupta, Brian C. Kluge, Kristoffer D. Fleming
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Patent number: 9176550Abstract: An apparatus may comprise a power management system. Other embodiments are described and claimed.Type: GrantFiled: December 23, 2010Date of Patent: November 3, 2015Assignee: INTEL CORPORATIONInventors: Biswajit Sur, Eric Distefano, James G. Hermerding, II, Eugene P. Matter, John P. Wallace, Guy M. Therien
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Publication number: 20140189404Abstract: An apparatus includes logic to control heat generation in a device. The device to operate ate leas in one of a first state and a second state, wherein the device to consume more power in the first state than in the second state. The device to connect to a network at least for a portion of time while in the second state. The logic to select a plurality of thermal control solutions to decrease the generation of heat in the device in the second state, the selected thermal control solution to be performed while the device is in the second state to reduce the generated heat to below a predetermined level.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Biswajit SUR, Thomas E. Walsh, Ajay G. Gupta, Brian C. Kluge, Kristoffer D. Fleming
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Publication number: 20120166842Abstract: An apparatus may comprise a power management system. Other embodiments are described and claimed.Type: ApplicationFiled: December 23, 2010Publication date: June 28, 2012Inventors: Biswajit Sur, Eric Distefano, James G. Hermerding, II, Eugene P. Matter, John P. Wallace, Guy M. Therien
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Patent number: 7242088Abstract: An apparatus and method for releasing pressure existing within a package comprising a substrate to which a die is attached to provide electrical connections between the die and the exterior of the package, a lid, and sealant disposed between the substrate and the lid in a pattern with at least one break in the pattern.Type: GrantFiled: December 29, 2000Date of Patent: July 10, 2007Assignee: Intel CorporationInventors: Sudipto Neogi, Biswajit Sur, Boon Seng Tan, Chris Rumer
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Patent number: 7220624Abstract: An apparatus and method for releasing pressure existing within a package comprising a substrate to which a die is attached to provide electrical connections between the die and the exterior of the package, a lid, and sealant disposed between the substrate and the lid in a pattern with at least one break in the pattern.Type: GrantFiled: June 29, 2005Date of Patent: May 22, 2007Assignee: Intel CorporationInventors: Sudipto Neogi, Biswajit Sur, Boon Seng Tan, Chris Rumer
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Patent number: 7174060Abstract: A method and apparatus that includes a first waveguide segment that differentially changes the amplitude of the light relative to a first polarization orientation, a thickness of oriented liquid crystal or other birefringent material sufficient to delay one polarization component one-half wavelength relative to another, and a second waveguide segment that also differentially changes the amplitude of the light based on the polarization orientation. Also, an apparatus that includes a thin polarization converter that includes a thin first substrate that is substantially transparent to a wavelength of light, and a birefringent material deposited on one or more surfaces of the first substrate and oriented such that the polarization converter forms a half-wavelength birefringent plate for the light. Also, an apparatus having a first substrate surface, a second substrate surface, and a liquid crystal material between the first and second substrate surfaces to form a polarization converter.Type: GrantFiled: July 26, 2005Date of Patent: February 6, 2007Assignee: Intel CorporationInventors: Nagesh K. Vodrahalli, Achintya K. Bhowmik, Connie C. Liu, Takaharu Fujiyama, Kenji Takahashi, Biswajit Sur
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Patent number: 7132313Abstract: A semiconductor chip is shown containing an integral heat spreading layer that more effectively transmits heat from the die to ambient as a result of spreading the heat out on the die over a larger cross sectional area. Local hot spots are minimized which allows the semiconductor chip to operate at a higher frequency for a given upper threshold temperature. Also shown is a method of manufacturing such a semiconductor chip, and the associated method of cooling a semiconductor chip.Type: GrantFiled: November 25, 2003Date of Patent: November 7, 2006Assignee: Intel CorporationInventors: Michael O'Connor, Kevin J. Haley, Biswajit Sur
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Patent number: 7091063Abstract: To accommodate high power densities associated with high performance integrated circuits, heat is dissipated from a surface of a die through a solderable thermal interface to a lid or integrated heat spreader. In one embodiment, the die is mounted on an organic substrate using a C4 and land grid array arrangement. In order to maximize thermal dissipation from the die while minimizing warpage of the package when subjected to heat, due to the difference in thermal coefficients of expansion between the die and the organic substrate, a thermal interface is used that has a relatively low melting point in addition to a relatively high thermal conductivity. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system, are also described.Type: GrantFiled: February 9, 2004Date of Patent: August 15, 2006Assignee: Intel CorporationInventors: Biswajit Sur, Nagesh Vodrahalli, Thomas Workman
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Patent number: 7065273Abstract: A flat-top arrayed waveguide grating with wideband transmission spectrum may be produced by integrating a series of directional couplers to the output slab waveguide coupler of a dual channel-spacing arrayed waveguide grating having Gaussian spectral profile. The primary channel spacing of the Gaussian arrayed waveguide grating determines the spectral width of the resultant wideband device, whereas the secondary channel spacing determines the wavelength separation between the adjacent output channels. In such a structure, a wideband or flat transmission spectral profile may be achieved without excessive losses.Type: GrantFiled: June 20, 2003Date of Patent: June 20, 2006Assignee: Intel CorporationInventors: Achintya K. Bhowmik, Biswajit Sur
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Publication number: 20060018585Abstract: A method and apparatus that includes a first waveguide segment that differentially changes the amplitude of the light relative to a first polarization orientation, a thickness of oriented liquid crystal or other birefringent material sufficient to delay one polarization component one-half wavelength relative to another, and a second waveguide segment that also differentially changes the amplitude of the light based on the polarization orientation. Also, an apparatus that includes a thin polarization converter that includes a thin first substrate that is substantially transparent to a wavelength of light, and a birefringent material deposited on one or more surfaces of the first substrate and oriented such that the polarization converter forms a half-wavelength birefringent plate for the light. Also, an apparatus having a first substrate surface, a second substrate surface, and a liquid crystal material between the first and second substrate surfaces to form a polarization converter.Type: ApplicationFiled: July 26, 2005Publication date: January 26, 2006Inventors: Nagesh Vodrahalli, Achintya Bhowmik, Connie Liu, Takaharu Fujiyama, Kenji Takahashi, Biswajit Sur
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Patent number: 6982192Abstract: An integrated circuit package which has a thermal epoxy that can be attached to an integrated circuit and a thermal element. The thermal epoxy can be cured with energy at a microwave frequency. Curing the thermal epoxy with microwave energy can minimize package warpage during the curing process.Type: GrantFiled: December 30, 1999Date of Patent: January 3, 2006Assignee: Intel CorporationInventors: Nagesh Vodrahalli, Biswajit Sur
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Publication number: 20050253254Abstract: An apparatus and method for releasing pressure existing within a package comprising a substrate to which a die is attached to provide electrical connections between the die and the exterior of the package, a lid, and sealant disposed between the substrate and the lid in a pattern with at least one break in the pattern.Type: ApplicationFiled: June 29, 2005Publication date: November 17, 2005Inventors: Sudipto Neogi, Biswajit Sur, Boon Tan, Chris Rumer
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Patent number: 6928200Abstract: A method and apparatus that includes a first waveguide segment that differentially changes the amplitude of the light relative to a first polarization orientation, a thickness of oriented liquid crystal or other birefringent material sufficient to delay one polarization component one-half wavelength relative to another, and a second waveguide segment that also differentially changes the amplitude of the light based on the polarization orientation. Also, an apparatus that includes a thin polarization converter that includes a thin first substrate that is substantially transparent to a wavelength of light, and a birefringent material deposited on one or more surfaces of the first substrate and oriented such that the polarization converter forms a half-wavelength birefringent plate for the light. Also, an apparatus having a first substrate surface, a second substrate surface, and a liquid crystal material between the first and second substrate surfaces to form a polarization converter.Type: GrantFiled: October 7, 2002Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Nagesh K. Vodrahalli, Achintya K. Bhowmik, Connie C. Liu, Takaharu Fujiyama, Kenji Takahashi, Biswajit Sur
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Publication number: 20050047722Abstract: A flat-top arrayed waveguide grating with wideband transmission spectrum may be produced by integrating a series of directional couplers to the output slab waveguide coupler of a dual channel-spacing arrayed waveguide grating having Gaussian spectral profile. The primary channel spacing of the Gaussian arrayed waveguide grating determines the spectral width of the resultant wideband device, whereas the secondary channel spacing determines the wavelength separation between the adjacent output channels. In such a structure, a wideband or flat transmission spectral profile may be achieved without excessive losses.Type: ApplicationFiled: June 20, 2003Publication date: March 3, 2005Inventors: Achintya Bhowmik, Biswajit Sur
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Patent number: 6860642Abstract: An optical connector comprises an optical circuit and a package casing. The package casing has an integrated modular optical connector, which has multiple optical waveguides.Type: GrantFiled: March 14, 2002Date of Patent: March 1, 2005Assignee: Intel CorporationInventors: Nagesh K. Vodrahalli, Jaiom S. Sambyal, Biswajit Sur
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Publication number: 20040155329Abstract: To accommodate high power densities associated with high performance integrated circuits, heat is dissipated from a surface of a die through a solderable thermal interface to a lid or integrated heat spreader. In one embodiment, the die is mounted on an organic substrate using a C4 and land grid array arrangement. In order to maximize thermal dissipation from the die while minimizing warpage of the package when subjected to heat, due to the difference in thermal coefficients of expansion between the die and the organic substrate, a thermal interface is used that has a relatively low melting point in addition to a relatively high thermal conductivity. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system, are also described.Type: ApplicationFiled: February 9, 2004Publication date: August 12, 2004Applicant: Intel CorporationInventors: Biswajit Sur, Nagesh K. Vodrahalli, Thomas Workman
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Publication number: 20040104014Abstract: A semiconductor chip is shown containing an integral heat spreading layer that more effectively transmits heat from the die to ambient as a result of spreading the heat out on the die over a larger cross sectional area. Local hot spots are minimized which allows the semiconductor chip to operate at a higher frequency for a given upper threshold temperature. Also shown is a method of manufacturing such a semiconductor chip, and the associated method of cooling a semiconductor chip.Type: ApplicationFiled: November 25, 2003Publication date: June 3, 2004Applicant: Intel Corporation.Inventors: Michael O'Connor, Kevin J. Haley, Biswajit Sur