Abstract: The present invention provides a control method of an electronic device, wherein the control method includes the steps of: generating a MAC frame; performing a specific encoding operation on a specific field of the MAC frame to generate a parity; using the parity to replace part of content of the specific field; and generating a packet according to the MAC frame for sending to another electronic device.

Abstract: The present invention provides a control method of an electronic device, wherein the control method includes the steps of: generating a MAC frame; performing a specific encoding operation on a specific field of the MAC frame to generate a parity; using the parity to replace part of content of the specific field; and generating a packet according to the MAC frame for sending to another electronic device.

Abstract: Disclosed is a baud rate tracking and compensation apparatus comprising: a clock generating component generating a clock; a sampling circuit sampling a reception signal according to the clock and thereby generating a sampled result, and the sampling circuit generating a transition notification signal when the sampled result indicates a transition of the reception signal; a clock counting circuit counting cycles of the clock between a first transition of the reception signal and a second transition of the reception signal according to the clock and the transition notification signal; a bit counting circuit counting bit(s) between the first transition and the second transition according to the clock and a bit cycle; and a calculation circuit dividing the number of the cycles by the number of the bit(s) to obtain a calculation value, and then updating the bit cycle according to the calculation value.

Abstract: Disclosed is a baud rate tracking and compensation apparatus comprising: a clock generating component generating a clock; a sampling circuit sampling a reception signal according to the clock and thereby generating a sampled result, and the sampling circuit generating a transition notification signal when the sampled result indicates a transition of the reception signal; a clock counting circuit counting cycles of the clock between a first transition of the reception signal and a second transition of the reception signal according to the clock and the transition notification signal; a bit counting circuit counting bit(s) between the first transition and the second transition according to the clock and a bit cycle; and a calculation circuit dividing the number of the cycles by the number of the bit(s) to obtain a calculation value, and then updating the bit cycle according to the calculation value.