Patents by Inventor Bjarni Benjaminsson

Bjarni Benjaminsson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11869616
    Abstract: A system and method for centrally logging and aggregating miscompares on chip during a memory test. The method includes performing, by a built-in self-test (BIST) unit of a memory device, a memory test on one or more memory banks of the memory device using a first algorithm. The method includes generating miscompare results responsive to performing the memory test on the one or more memory banks of the memory device. The method includes determining failure diagnostic information based on the miscompare results. The method includes generating an error packet comprising the failure diagnostic information and the miscompare results. The method includes placing the error packet in a queue of a plurality of error packets to generate a queued error packet.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: January 9, 2024
    Assignee: Cypress Semiconductor Corporation
    Inventors: Senwen Kan, Andrew Payne, Jeffrey W Gossett, Michael Joseph Pluhta, Richard A Rodell, Jr., Bjarni Benjaminsson
  • Publication number: 20230142759
    Abstract: A system and method for centrally logging and aggregating miscompares on chip during a memory test. The method includes performing, by a built-in self-test (BIST) unit of a memory device, a memory test on one or more memory banks of the memory device using a first algorithm. The method includes generating miscompare results responsive to performing the memory test on the one or more memory banks of the memory device. The method includes determining failure diagnostic information based on the miscompare results. The method includes generating an error packet comprising the failure diagnostic information and the miscompare results. The method includes placing the error packet in a queue of a plurality of error packets to generate a queued error packet.
    Type: Application
    Filed: November 11, 2021
    Publication date: May 11, 2023
    Applicant: Cypress Semiconductor Corporation
    Inventors: Senwen Kan, Andrew Payne, Jeffrey W Gossett, Michael Joseph Pluhta, Richard A. Rodell, JR., Bjarni Benjaminsson