Patents by Inventor Bjorn Freeman-Benson

Bjorn Freeman-Benson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7979263
    Abstract: A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit. The exemplary system includes a scheduler, a memory, and a compiler. The scheduler is capable of scheduling a selected algorithm with a plurality of adaptive computing descriptive objects to produce a scheduled algorithm and a selected adaptive computing circuit version. The memory is utilized to store the plurality of adaptive computing descriptive objects and a plurality of adaptive computing circuit versions generated during the scheduling process. The selected adaptive computing circuit version is converted into a hardware description language, for fabrication into the adaptive computing integrated circuit.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: July 12, 2011
    Assignee: QST Holding, LLC
    Inventors: Paul L. Master, Eugene Hogenauer, Bicheng William Wu, Dan MingLun Chuang, Bjorn Freeman Benson
  • Publication number: 20090119480
    Abstract: A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit. The exemplary system includes a scheduler, a memory, and a compiler. The scheduler is capable of scheduling a selected algorithm with a plurality of adaptive computing descriptive objects to produce a scheduled algorithm and a selected adaptive computing circuit version. The memory is utilized to store the plurality of adaptive computing descriptive objects and a plurality of adaptive computing circuit versions generated during the scheduling process. The selected adaptive computing circuit version is converted into a hardware description language, for fabrication into the adaptive computing integrated circuit.
    Type: Application
    Filed: January 8, 2009
    Publication date: May 7, 2009
    Applicant: QST Holdings, LLC
    Inventors: Paul L. Master, Eugene Hogenauer, Bicheng William (William) Wu, Dan MingLun Chuang, Bjorn Freeman-Benson
  • Patent number: 7478031
    Abstract: A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit. The exemplary system includes a scheduler, a memory, and a compiler. The scheduler is capable of scheduling a selected algorithm with a plurality of adaptive computing descriptive objects to produce a scheduled algorithm and a selected adaptive computing circuit version. The memory is utilized to store the plurality of adaptive computing descriptive objects and a plurality of adaptive computing circuit versions generated during the scheduling process. The selected adaptive computing circuit version is converted into a hardware description language, for fabrication into the adaptive computing integrated circuit.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: January 13, 2009
    Assignee: QST Holdings, LLC
    Inventors: Paul L. Master, Eugene Hogenauer, Bicheng William Wu, Dan MingLun Chuang, Bjorn Freeman-Benson
  • Publication number: 20040093601
    Abstract: A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit. The exemplary system includes a scheduler, a memory, and a compiler. The scheduler is capable of scheduling a selected algorithm with a plurality of adaptive computing descriptive objects to produce a scheduled algorithm and a selected adaptive computing circuit version. The memory is utilized to store the plurality of adaptive computing descriptive objects and a plurality of adaptive computing circuit versions generated during the scheduling process. The selected adaptive computing circuit version is converted into a hardware description language, for fabrication into the adaptive computing integrated circuit.
    Type: Application
    Filed: November 7, 2002
    Publication date: May 13, 2004
    Applicant: QuickSilver Technology, Inc.
    Inventors: Paul L. Master, Eugene Hogenauer, Bicheng William Wu, Dan MingLun Chuang, Bjorn Freeman-Benson