Patents by Inventor Bjorn K. A. Zetterlund

Bjorn K. A. Zetterlund has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor devices with enhanced electromigration performance
    Patent number: 9362229
    Abstract: Semiconductor devices with enhanced electromigration performance and methods of manufacture are disclosed. The method includes forming at least one metal line in electrical contact with a device. The method further includes forming at least one staple structure in electrical contact with the at least one metal line. The at least one staple structure is formed such that electrical current passing through the at least one metal line also passes through the at least staple structure to reduce electromigration issues.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: June 7, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jeffrey P. Gambino, David L. Harame, Baozhen Li, Timothy D. Sullivan, Bjorn K. A. Zetterlund
  • SEMICONDUCTOR DEVICES WITH ENHANCED ELECTROMIGRATION PERFORMANCE
    Publication number: 20150035158
    Abstract: Semiconductor devices with enhanced electromigration performance and methods of manufacture are disclosed. The method includes forming at least one metal line in electrical contact with a device. The method further includes forming at least one staple structure in electrical contact with the at least one metal line. The at least one staple structure is formed such that electrical current passing through the at least one metal line also passes through the at least staple structure to reduce electromigration issues.
    Type: Application
    Filed: October 16, 2014
    Publication date: February 5, 2015
    Inventors: Jeffrey P. GAMBINO, David L. HARAME, Baozhen LI, Timothy D. SULLIVAN, Bjorn K.A. ZETTERLUND
  • Method of manufacturing an enhanced electromigration performance hetero-junction bipolar transistor
    Patent number: 8901738
    Abstract: Semiconductor devices with enhanced electromigration performance and methods of manufacture are disclosed. The method includes forming at least one metal line in electrical contact with a device. The method further includes forming at least one staple structure in electrical contact with the at least one metal line. The at least one staple structure is formed such that electrical current passing through the at least one metal line also passes through the at least staple structure to reduce electromigration issues.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, David L. Harame, Baozhen Li, Timothy D. Sullivan, Bjorn K. A. Zetterlund
  • SEMICONDUCTOR DEVICES WITH ENHANCED ELECTROMIGRATION PERFORMANCE
    Publication number: 20140131878
    Abstract: Semiconductor devices with enhanced electromigration performance and methods of manufacture are disclosed. The method includes forming at least one metal line in electrical contact with a device. The method further includes forming at least one staple structure in electrical contact with the at least one metal line. The at least one staple structure is formed such that electrical current passing through the at least one metal line also passes through the at least staple structure to reduce electromigration issues.
    Type: Application
    Filed: November 12, 2012
    Publication date: May 15, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Gambino, David L. Harame, Baozhen Li, Timothy D. Sullivan, Bjorn K. A. Zetterlund
  • Precision resistor in self-aligned silicided MOS process
    Patent number: 5134088
    Abstract: A precision resistor is formed in an integrated circuit by a diffused region created at the same time as transistor source/drain regions. In a CMOS process, this N-type resistor region is formed in an N-well, as is used for P-channel transistors. The resistor formed using a deposited oxide layer as a mask, and this oxide layer is also used to create sidewall spacers for the transistor gates. The sidewall spacers are used in creating self-aligned silicided areas over the source/drain regions, self-aligned with the gates, and the silicide is also used for contact areas for the resistor. The value of the resistor is defined by the width of the deposited oxide layer left as a mask, but this does not require any critical alignment steps.
    Type: Grant
    Filed: April 27, 1990
    Date of Patent: July 28, 1992
    Assignee: Digital Equipment Corporation
    Inventor: Bjorn K. A. Zetterlund