Patents by Inventor Bjorn P. Christensen
Bjorn P. Christensen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11422611Abstract: A method for facilitating adaptive frequency in a processor having a plurality of cores. The method can include conducting tests on the processor; determining, via the processor testing system, default parameters for operating one or more of the cores, wherein the default parameters are based on results of the tests and cause one or more of the cores to operate within production yield goals of the processor; determining alternative parameters for operating one or more of the cores, wherein the alternative parameters are based on results of the test and cause one or more of the cores to operate outside production yield goals of the processor, and wherein the alternative parameters are usable to reconfigure one or more of the cores after an initial operation per the default parameters; and writing the default parameters and the alternative parameters to a production data storage of the processor.Type: GrantFiled: November 8, 2019Date of Patent: August 23, 2022Assignee: International Business Machines CorporationInventors: Nathaniel R. Chadwick, Bjorn P. Christensen, James M. Crafts, Allen R. Hall, Kevin F. Reick, Jon Robert Tetzloff
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Publication number: 20200073459Abstract: A method for facilitating adaptive frequency in a processor having a plurality of cores. The method can include conducting tests on the processor; determining, via the processor testing system, default parameters for operating one or more of the cores, wherein the default parameters are based on results of the tests and cause one or more of the cores to operate within production yield goals of the processor; determining alternative parameters for operating one or more of the cores, wherein the alternative parameters are based on results of the test and cause one or more of the cores to operate outside production yield goals of the processor, and wherein the alternative parameters are usable to reconfigure one or more of the cores after an initial operation per the default parameters; and writing the default parameters and the alternative parameters to a production data storage of the processor.Type: ApplicationFiled: November 8, 2019Publication date: March 5, 2020Inventors: Nathaniel R. Chadwick, Bjorn P. Christensen, James M. Crafts, Allen R. Hall, Kevin F. Reick, Jon Robert Tetzloff
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Patent number: 10509457Abstract: A processor can have a plurality of cores. A first core processor of a first core can read one or more values of a default parameter set. The first core can be operated in accordance with a first operating characteristic based, at least in part, on the one or more values of the default parameter set. The first core processor can receive an indication to change the operating characteristic of the first core processor. In response to receiving the indication to change the operating characteristic, a signal can be issued to the first core processor to reset. In response to the reset, the first core processor can read one or more values of an alternative parameter set. The first core processor can then be operated in accordance with a second operating characteristic based, at least in part, on the one or more values of the alternative parameter set.Type: GrantFiled: April 6, 2017Date of Patent: December 17, 2019Assignee: International Business Machines CorporationInventors: Nathaniel R. Chadwick, Bjorn P. Christensen, James M. Crafts, Allen R. Hall, Kevin F. Reick, Jon Robert Tetzloff
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Publication number: 20180292878Abstract: A processor can have a plurality of cores. A first core processor of a first core can read one or more values of a default parameter set. The first core can be operated in accordance with a first operating characteristic based, at least in part, on the one or more values of the default parameter set. The first core processor can receive an indication to change the operating characteristic of the first core processor. In response to receiving the indication to change the operating characteristic, a signal can be issued to the first core processor to reset. In response to the reset, the first core processor can read one or more values of an alternative parameter set. The first core processor can then be operated in accordance with a second operating characteristic based, at least in part, on the one or more values of the alternative parameter set.Type: ApplicationFiled: April 6, 2017Publication date: October 11, 2018Inventors: Nathaniel R. Chadwick, Bjorn P. Christensen, James M. Crafts, Allen R Hall, Kevin F. Reick, Jon Robert Tetzloff
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Patent number: 9971393Abstract: The embodiments described herein relate to dynamically detecting a frequency change condition for microprocessor performance. An instruction is received, and a frequency change condition associated with the received instruction is dynamically detected. A frequency modulation is performed in response to the dynamic detection. The frequency modulation includes selecting a second frequency for optimal instruction processing different from a first frequency, the first frequency being a default operating frequency of the microprocessor. Execution of the instruction is completed at the second frequency. Accordingly, incoming execution instructions are logically analyzed, and the processor frequency is selectively modified based on associated instruction conditions.Type: GrantFiled: December 16, 2015Date of Patent: May 15, 2018Assignee: International Business Machines CorporationInventors: Bjorn P. Christensen, Victor Zyuban
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Publication number: 20170177064Abstract: The embodiments described herein relate to dynamically detecting a frequency change condition for microprocessor performance. An instruction is received, and a frequency change condition associated with the received instruction is dynamically detected. A frequency modulation is performed in response to the dynamic detection. The frequency modulation includes selecting a second frequency for optimal instruction processing different from a first frequency, the first frequency being a default operating frequency of the microprocessor. Execution of the instruction is completed at the second frequency. Accordingly, incoming execution instructions are logically analyzed, and the processor frequency is selectively modified based on associated instruction conditions.Type: ApplicationFiled: December 16, 2015Publication date: June 22, 2017Applicant: International Business Machines CorporationInventors: Bjorn P. Christensen, Victor Zyuban
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Patent number: 8127116Abstract: A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.Type: GrantFiled: April 3, 2009Date of Patent: February 28, 2012Assignee: International Business Machines CorporationInventors: Saiful Islam, Mary D. Brown, Bjorn P. Christensen, Sam G. Chu, Robert A. Cordes, Maureen A. Delaney, Jafar Nahidi, Joel A. Silberman
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Publication number: 20100257336Abstract: A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.Type: ApplicationFiled: April 3, 2009Publication date: October 7, 2010Applicant: International Business Machines CorporationInventors: Saiful Islam, Mary D. Brown, Bjorn P. Christensen, Sam G. Chu, Robert A. Cordes, Maureen A. Delaney, Jafar Nahidi, Joel A. Silberman