Patents by Inventor Bjorn Vandecasteele

Bjorn Vandecasteele has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10910342
    Abstract: An example embodiment may include a method for placing on a carrier substrate a semiconductor device. The method may include providing a semiconductor substrate comprising a rectangular shaped assist chip, which may include at least one semiconductor device surrounded by a metal-free border. The method may also include dicing the semiconductor substrate to singulate the rectangular shaped assist chip. The method may further include providing a carrier substrate having adhesive thereon. The method may additionally include transferring to and placing on the carrier substrate the rectangular shaped assist chip, thereby contacting the adhesive with the rectangular shaped assist chip at least at a location of the semiconductor device. The method may finally include singulating the semiconductor device, while remaining attached to the carrier substrate by the adhesive, by removing a part of rectangular shaped assist chip other than the semiconductor device.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: February 2, 2021
    Assignees: IMEC VZW, UNIVERSITEIT GENT
    Inventors: Maria Op de Beeck, Bjorn Vandecasteele
  • Publication number: 20180161065
    Abstract: A surgical insertion device is disclosed, comprising an elongated central flat region tapering from one distal end having a device area, configured to receive an electronic device, towards the opposite distal end having a sharp tip.
    Type: Application
    Filed: December 6, 2017
    Publication date: June 14, 2018
    Applicants: Imec VZW, Universiteit Gent
    Inventors: Maria Op de Beeck, Bjorn Vandecasteele, Dries Braeken
  • Publication number: 20180166416
    Abstract: An example embodiment may include a method for placing on a carrier substrate a semiconductor device. The method may include providing a semiconductor substrate comprising a rectangular shaped assist chip, which may include at least one semiconductor device surrounded by a metal-free border. The method may also include dicing the semiconductor substrate to singulate the rectangular shaped assist chip. The method may further include providing a carrier substrate having adhesive thereon. The method may additionally include transferring to and placing on the carrier substrate the rectangular shaped assist chip, thereby contacting the adhesive with the rectangular shaped assist chip at least at a location of the semiconductor device. The method may finally include singulating the semiconductor device, while remaining attached to the carrier substrate by the adhesive, by removing a part of rectangular shaped assist chip other than the semiconductor device.
    Type: Application
    Filed: December 8, 2017
    Publication date: June 14, 2018
    Applicants: IMEC VZW, Universiteit Gent
    Inventors: Maria Op de Beeck, Bjorn Vandecasteele
  • Patent number: 9673382
    Abstract: In order to solve the problem of the generation of the interspace between layers, the present invention provides an actuator including: a conductive polymer layer; an ambient temperature molten salt layer; and an opposite electrode layer; wherein the ambient temperature molten salt layer is interposed between the conductive polymer layer and the opposite electrode layer, the ambient temperature molten salt layer includes an adhesive layer in the inside thereof; one surface of the adhesive layer adheres to the conductive polymer layer; and the other surface of the adhesive layer adheres to the opposite electrode layer.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: June 6, 2017
    Assignees: Panasonic Corporation, IMEC vzw, Universiteit Gent
    Inventors: Maki Hiraoka, Paolo Fiorini, Bjorn Vandecasteele
  • Patent number: 6555414
    Abstract: The present invention is related to a flip-chip-on-board (FCOB) assembly technology applicable for mounting large chips with high I/O count or small pitch, mounted on low-cost or low-grade substrates. The assembly technology uses both an isotropically conductive adhesive (ICA) and a non-conductive material (NCA) in the same assembly cycle. The thermocompression step establishes at the same time the electrical and mechanical interconnections and the curing of the adhesives.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: April 29, 2003
    Assignee: Interuniversitair Microelektronica Centrum, vzw
    Inventors: Jan Vanfleteren, Sergei Stoukach, Bjorn Vandecasteele