Abstract: A method and apparatus for initializing both processors in a master/checker fault detecting microprocessor. A microcode initialization routine is run by each processor upon reset of both of the processors in the pair. The routines cause each processor to be initialized, such that the two processors complete initialization at the same time and operate in a lock-step manner.

Abstract: A cache control method and mechanism for an external cache memory having multiple cache lines using interagent communications to cause invalidating the external cache memory, flushing the external cache memory and/or changing the coherency state of lines in the external cache memory.

Abstract: A prefetching replicated instruction stream machine (PRISM) computer architecture which provides sustained instruction stream performance comparable to peak performance in computer systems with instruction pipelines operates by partitioning, prior to execution, a computer program to be executed into instruction segments based on entry point and branch target instructions defining the flow changes within the program; storing selected segments in a plurality of instruction decoding units (IDUs) such that all instructions that potentially could be needed when the next instruction is executed by a central processing unit (CPU) are stored in the IDUs, and such that no single IDU contains both a segment having a branch taken instruction and a segment containing a branch not taken instruction for the same branch instruction; simultaneously decoding in a predetermined order the instruction segments stored in each IDU; and selectively communicating instructions decoded by the IDUs to the CPU in response to the value o